Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

Abstract

This paper details the formal verification of WARP-V, an open-source RISC-V core generator developed using the timing-abstract, transaction-level TL-Verilog methodology. The verification employed the established riscv-formal framework, investigating the synergy between transaction-level design and formal methods. The study found that TL-Verilog significantly simplified the creation of a verification harness, which, due to the abstract modeling, successfully works across all configurations of the WARP-V RISC-V core.

Report

Key Highlights

• Target: Formal verification of WARP-V, an open-source, configurable RISC-V CPU core generator.
• Methodology Synergy: Exploration of the integration between Transaction-Level Design (TL-Verilog) and formal verification.
• Verification Vehicle: The verification relied on the existing riscv-formal framework for RISC-V architecture checking.
• Productivity Gain: TL-Verilog's modeling techniques simplified the process of creating the verification harness.
• Universal Harness: The resulting verification harness is timing-abstract and functions identically across all potential RISC-V configurations generated by WARP-V.

Technical Details

• Core Generator: WARP-V, implemented in TL-Verilog, is capable of generating various RISC-V core configurations.
• Design Language: TL-Verilog, which enables timing-abstract and transaction-level logic modeling, contributing to recognized productivity gains in logic design.
• Formal Verification Framework: riscv-formal, a specialized tool designed to formally prove the correctness of RISC-V processor designs against the instruction set architecture (ISA) specification.
• Harness Abstraction: The transaction-level nature of the WARP-V model greatly streamlined the interface (harness) connecting the core to the demanding riscv-formal verification environment.

Implications

• Validation of TL-Verilog: This work validates that the productivity gains offered by TL-Verilog extend beyond design creation and into the crucial phase of formal verification.
• Enhanced RISC-V Reliability: By proving that highly configurable RISC-V core generators like WARP-V can be rigorously verified using existing formal tools (like riscv-formal), the robustness of the open-source hardware ecosystem is significantly increased.
• Verification Efficiency: The demonstration that a single, universal verification harness can serve all configurations of a core simplifies the overall design flow, reducing the maintenance overhead traditionally associated with verifying configurable IP.