Floating Point HUB Adder for RISC-V Sargantana Processor

Abstract

This paper introduces a tailored Floating Point HUB Adder specifically implemented within the Sargantana RISC-V processor. The HUB format is utilized as an emerging technique to improve hardware requirements and reduce processing time associated with the 'round to nearest' operation. This work demonstrates the integration of advanced floating-point arithmetic methods into the rapidly expanding open-source RISC-V Instruction Set Architecture.

Report

Key Highlights

• Novel Component: Presents a new Floating Point HUB Adder design.
• Target Platform: The adder is implemented and tailored for the Sargantana RISC-V processor.
• Optimization Goal: The HUB format is employed primarily to reduce hardware complexity and processing time, specifically when executing the common 'round to nearest' operation.
• Architectural Context: The work combines an emerging arithmetic technique (HUB format) with the popular open-source RISC-V ISA.

Technical Details

• Core Technology: HUB format, defined as a technique for improving efficiency in floating-point operations requiring rounding.
• Functionality: Floating Point Adder logic.
• Integration: Customized integration into the Sargantana processor, which is built on the RISC-V instruction set.
• Arithmetic Focus: Direct optimization of the time and hardware footprint for the 'round to nearest' mechanism.

Implications

• RISC-V Performance: This research contributes concrete, optimized hardware designs (FPUs) to the RISC-V ecosystem, potentially leading to smaller, faster, or lower-power floating-point units in future RISC-V cores.
• Validation of HUB Format: The implementation provides practical validation for the HUB format as a viable technique for high-efficiency floating-point arithmetic.
• Hardware Innovation: By demonstrating optimized FP units, this work helps elevate RISC-V's competitiveness against proprietary ISAs in performance-critical applications like scientific computing and AI acceleration.