Abstract

This paper introduces an automated methodology for creating RISC-V Instruction Subset Processors (RISSPs) specifically tailored for power and area-constrained Extreme Edge applications, including those using flexible integrated circuits (FlexICs). The approach treats individual instructions as discrete, pre-verified hardware blocks, automatically stitching together only the components required by the target application domain. This customization yields substantial efficiency gains, achieving up to 43% area reduction and demonstrating an average of 40 times greater energy efficiency compared to the Serv 32-bit RISC-V processor.

Report

Structured Report: Flexing RISC-V Instruction Subset Processors to Extreme Edge

Key Highlights

• Target Domain: Focuses on designing highly efficient processors for "Extreme Edge" applications, which demand low area, low power, low cost, conformability, comfort, and sustainability.
• Core Innovation: Proposes an automated methodology for generating customized RISC-V Instruction Subset Processors (RISSPs) based only on the instructions required by the application.
• Efficiency Gains (Synthesis): RISSPs achieve between 8% to 43% reduction in area and 3% to 30% reduction in power compared to a processor supporting the full RISC-V ISA.
• Energy Benchmark: The generated processors are approximately 40 times more energy efficient on average than Serv, widely known as one of the world's smallest 32-bit RISC-V processors.
• Physical Implementation: When implemented as Flexible Integrated Circuits (FlexICs), the extreme edge RISSPs demonstrate up to 42% area savings and 21% power savings.

Technical Details

• Processor Type: RISC-V Instruction Subset Processors (RISSPs).
• Implementation Technology: Flexible Integrated Circuits (FlexICs), intended to replace traditional silicon-based electronics in conformable and sustainable extreme edge devices.
• Design Methodology: An automated approach where verification is integral. Each instruction in the RISC-V ISA is represented as a discrete, fully functional, pre-verified hardware block.
• Customization Process: The methodology automatically synthesizes the custom processor by only stitching together the specific instruction hardware blocks required by a given application or defined set of applications (e.g., from the Embench benchmark suite).
• Evaluation: Performance was measured using three specific extreme edge applications and standard embedded applications from the Embench suite.

Implications

• Enabling Flexible Electronics: By specifically addressing the physical constraints of FlexICs (area and power), this methodology opens the door for RISC-V to become the dominant architecture in conformable and sustainable computing paradigms at the extreme edge.
• Design Efficiency: Treating instructions as pre-verified modular blocks significantly streamlines the verification stage and accelerates the design process for application-specific integrated circuits (ASICs).
• RISC-V Ecosystem Expansion: The dramatic gains in energy efficiency position RISC-V not just as a scalable architecture, but as the leading choice for ultra-low-power, customized embedded systems, significantly outperforming existing small core designs.
• Cost Reduction: The substantial area reduction (up to 43%) translates directly into lower manufacturing costs, which is critical for high-volume, low-margin extreme edge consumer applications.