FiCABU: A Fisher-Based, Context-Adaptive Machine Unlearning Processor for Edge AI

Abstract

FiCABU (Fisher-based Context-Adaptive Balanced Unlearning) is a novel software-hardware co-design that integrates efficient machine unlearning capabilities into a RISC-V edge AI processor. This system employs Context-Adaptive Unlearning, starting edits from back-end layers, and Balanced Dampening, which is scaled by depth to maintain the accuracy of retained data. FiCABU dramatically reduces computational overhead by up to 87.52% and minimizes energy consumption, making privacy-preserving AI practical for resource-constrained edge devices.

Report

Key Highlights

• Novelty: FiCABU is the first known specialized processor for Context-Adaptive Machine Unlearning (MU) designed for the strict power and computational budgets of Edge AI.
• Methodology: The system utilizes a dual-pronged approach: Context-Adaptive Unlearning (CAU) and Balanced Dampening (BD).
• Efficiency Gains: The approach reduces computation by up to 87.52% (ResNet-18) and 71.03% (ViT) compared to prior retraining-free baselines like Selective Synaptic Dampening (SSD).
• Energy Performance: An INT8 hardware prototype showed massive energy reduction, achieving as low as 0.13% of the SSD baseline energy consumption.
• Implementation: The entire solution is realized as a full RTL design integrated into a RISC-V edge AI processor framework, validated on an FPGA prototype and synthesized in 45 nm.

Technical Details

• Processor Core: Based on a RISC-V architecture tailored for Edge AI workloads.
• Architecture: FiCABU integrates specialized, lightweight IP blocks for Fisher estimation and weight dampening directly into a General Matrix Multiply (GEMM)-centric streaming pipeline.
• Context-Adaptive Unlearning (CAU): This method optimizes unlearning by initiating weight edits at the model's back-end layers and dynamically halting the process as soon as the target forgetting accuracy is achieved, reducing unnecessary computation.
• Balanced Dampening (BD): To prevent accuracy degradation on non-unlearned (retained) data, dampening strength is scaled layer-wise, according to the depth of the layer, preserving overall model utility.
• Validation: Tested on common models (ResNet-18 and ViT) and datasets (CIFAR-20, PinsFaceRecognition), demonstrating high retain accuracy while achieving random-guess forget accuracy.
• Fabrication/Quantization: Results include power analysis from a 45 nm synthesis and performance metrics from an INT8 hardware prototype.

Implications

• Enabling Edge Privacy: FiCABU provides a vital hardware mechanism for complying with regulations like the "right to be forgotten" directly at the edge, shifting the heavy burden of machine unlearning away from costly cloud retraining or impractical server-side processing.
• RISC-V Ecosystem Advancement: By integrating specialized MU acceleration IPs into a RISC-V core, the work significantly broadens the functional scope and appeal of RISC-V designs in the high-growth Edge AI sector, making RISC-V competitive for applications requiring real-time, privacy-aware data processing.
• Efficiency Standard: The achieved energy and computation reductions set a new state-of-the-art benchmark, proving that complex, utility-preserving model modifications (like unlearning) can be executed with minimal resource expenditure, suitable for battery-powered IoT devices.
• Hardware/Software Co-design: This successful implementation demonstrates the power of co-design, where specialized algorithmic improvements (CAU, BD) are seamlessly mapped onto optimized hardware pipelines (Fisher IP, Dampening IP), maximizing performance and efficiency.