FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors

Abstract

FERIVer is a novel FPGA-assisted System-on-Chip framework designed to accelerate the Register Transfer Level (RTL) verification of RISC-V processors. It resolves the traditional trade-off between speed and accuracy by leveraging an embedded CPU for cross-verification against synthesized hardware on programmable fabrics. This approach achieves a remarkable verification speed of 5 MIPS, delivering a 150x speedup over Xilinx XSim and a 35x boost compared to Verilator.

Report

Key Highlights

• FERIVer Framework: A proposed FPGA-assisted System-on-Chip (SoC) platform specifically designed for high-speed Register Transfer Level (RTL) verification of RISC-V processors.
• Performance Gain: Achieves a verification speed of 5 Million Instructions Per Second (MIPS).
• Speedup Benchmarks: This performance is 150x faster than the vendor-specific tool (Xilinx XSim) and 35x faster than the state-of-the-art open-source setup (Verilator).
• Efficiency: Enables flexible verification with high time and cost efficiency due to its low resource utilization.

Technical Details

• Architecture: Utilizes an FPGA-assisted SoC platform that combines instruction-level functional simulations with precise hardware emulations.
• Verification Methodology: Implements cross-verification by employing an embedded CPU to compare results against the processor hardware synthesized onto the programmable fabrics.
• Platform Specifics: The framework was developed and tested using the Zynq 7000 FPGA.
• Resource Consumption: The design exhibits high hardware efficiency, occupying less than 7% of the total hardware resources on the Zynq 7000 device.
• Goal: To accelerate the verification process of the RISC-V Instruction Set Architecture (ISA).

Implications

• Accelerated Development Cycle: The 150x speed improvement over commercial simulators fundamentally changes the feasibility of full regression testing and complex verification flows, drastically reducing time-to-market for RISC-V designs.
• Enhanced ISA Exploration: The framework provides a rapid, cost-effective platform for designers to explore new RISC-V instruction set architectures and custom extensions, addressing the challenge of verification efficiency.
• Accessibility: Its reliance on established Zynq platforms and its low hardware footprint (under 7%) makes advanced, high-speed emulation verification accessible to a wider range of development teams and budgets.