FeNN-DMA: A RISC-V SoC for SNN acceleration

Abstract

Spiking Neural Networks (SNNs), despite their energy efficiency, are poorly matched to conventional accelerators due to low arithmetic intensity. To address this, the authors introduce FeNN-DMA, a novel, fully-programmable RISC-V System-on-Chip tailored for SNN simulation on UltraScale+ FPGAs. This solution demonstrates comparable energy efficiency and resource usage to fixed-function accelerators while enabling the simulation of significantly larger and more complex models, achieving state-of-the-art accuracy on key neuromorphic benchmarks.

Report

Key Highlights

• Target Application: Acceleration of Spiking Neural Networks (SNNs), which are noted for being energy-efficient but having low arithmetic intensity compared to standard Artificial Neural Networks (ANNs).
• Innovation: Introduction of FeNN-DMA, a novel, fully-programmable RISC-V-based System-on-Chip (SoC) designed specifically for SNN simulation.
• Efficiency and Capacity: The SoC maintains comparable resource usage and energy requirements to state-of-the-art fixed-function SNN accelerators, yet is capable of simulating significantly larger and more complex SNN models.
• Performance: Demonstrated state-of-the-art classification accuracy on benchmarks including the Spiking Heidelberg Digits (SHD) and Neuromorphic MNIST tasks.

Technical Details

• Architecture Type: Custom System-on-Chip (SoC) named FeNN-DMA.
• Processor Core: Based on the RISC-V instruction set, making the system fully programmable.
• Target Hardware: Tailored for efficient implementation on modern UltraScale+ FPGAs.
• Workload Matching: Specifically designed to handle memory-bound SNN workloads, which are poorly suited for high arithmetic intensity hardware like GPUs/TPUs.

Implications

• Advancing SNN Adoption: By providing a highly efficient, yet programmable platform, FeNN-DMA lowers the barrier for simulating large and complex SNN models, promoting deeper research and deployment of energy-efficient neuromorphic computing solutions.
• RISC-V Specialization: This project validates the utility of RISC-V in highly specialized, domain-specific architectures (DSA), demonstrating its flexibility for custom silicon design targeting niche AI challenges where programmability is essential.
• Hardware Flexibility: The implementation leverages FPGAs to optimally handle the memory-bound nature of SNNs, proving that customizable, reconfigurable hardware is key to efficiently solving AI challenges where the arithmetic intensity is low.