FeNN: A RISC-V vector processor for Spiking Neural Network acceleration

Abstract

The FeNN processor is a novel RISC-V-based soft vector processor specifically tailored for simulating energy-efficient Spiking Neural Networks (SNNs) on FPGAs. Unlike mainstream accelerators, FeNN is optimized for the low arithmetic intensity of SNNs and is fully programmable for integration across edge-to-cloud applications. By leveraging techniques like stochastic rounding, a single FeNN core demonstrates superior performance, outperforming both an embedded GPU and the dedicated Loihi neuromorphic system in SNN classification speed.

Report

Key Highlights

• Novel Processor: FeNN is introduced as a novel RISC-V-based soft vector processor dedicated to the acceleration and simulation of Spiking Neural Networks (SNNs).
• Target Platform: It is specifically designed to run on FPGAs, leveraging their high off-chip memory bandwidth and large on-chip memory, which are suitable for the low arithmetic intensity of SNNs.
• Performance Benchmark: A single FeNN core demonstrated faster SNN classifier simulation performance compared to both an embedded GPU and the Intel Loihi neuromorphic system.
• Programmability: Unlike much dedicated neuromorphic hardware, FeNN is fully programmable, enabling flexible integration into standard computer systems ranging from edge devices to cloud infrastructure.
• Efficiency: The design achieves high numerical precision coupled with low hardware utilization through the implementation of stochastic rounding and saturation methods.

Technical Details

• Core Architecture: FeNN utilizes a soft vector processor architecture built upon the open standard RISC-V instruction set.
• Optimization Target: The design addresses the inefficiency of standard accelerators (GPUs, TPUs) when handling SNNs, whose computational workload is characterized by low arithmetic intensity.
• Precision Management: To minimize hardware resources without sacrificing accuracy, the processor employs specialized techniques: stochastic rounding and saturation.
• Deployment: FeNN is implemented as a soft processor, allowing it to be instantiated and customized on commercially available FPGAs.

Implications

• RISC-V Specialization: FeNN showcases the flexibility of the RISC-V architecture in creating highly specialized, domain-specific accelerators (DSAs). It proves that RISC-V can form the foundation for complex vector processing tailored explicitly for emerging AI models like SNNs.
• Democratization of Neuromorphic AI: By providing a fully programmable, RISC-V compliant platform for SNN acceleration, FeNN offers a general-purpose alternative to proprietary or highly restrictive dedicated neuromorphic chips, potentially accelerating SNN research and adoption.
• FPGA Relevance: This work reinforces the strategic importance of FPGAs in the AI hardware ecosystem, particularly for energy-efficient computing at the edge, where SNNs promise drastic energy reductions.
• Hardware Efficiency for SNNs: FeNN's performance superiority over both conventional embedded GPUs and specialized systems like Loihi suggests a viable and resource-efficient path for realizing the energy-saving potential of SNNs in real-world applications.