Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks

Abstract

This paper introduces Fast Selective Flushing (FaSe), a novel hardware/software countermeasure designed to mitigate contention-based cache timing attacks efficiently. FaSe utilizes a RISC-V ISA extension (one flush instruction) and minimal cache modifications to selectively flush only necessary cache lines. This approach significantly reduces time overhead by up to 42% compared to methods using slow, naive full flushing while maintaining effective security mitigation with less than 1% hardware cost.

Report

Key Highlights

• Target Mitigation: The solution addresses contention-based cache timing attacks (side channels) that exploit the performance benefits of modern caches.
• Novel Countermeasure: Introduction of Fast Selective Flushing (FaSe), a hardware/software collaborative approach.
• Performance Gain: FaSe reduces the time overhead associated with flushing countermeasures significantly: 36% for user programs and 42% for the operating system, compared to naive full flushing.
• Low Overhead: The necessary hardware modification requires less than 1% additional hardware overhead.
• Applicability: Unlike some existing methods (like partitioning/randomization), FaSe is suitable for mitigating attacks involving the L1 data cache.

Technical Details

• Architecture Modification: FaSe requires modifications to the cache structure, specifically the addition of state bits and control logic.
• Instruction Set Extension (ISA): The mechanism relies on adding a single new flush instruction to the ISA, allowing software to selectively trigger the optimized flushing process.
• Core Implementation: The solution was implemented and evaluated on the RISC-V Rocket Core/Chip architecture.
• Evaluation Platform: Testing was conducted on a Xilinx FPGA running both user programs and the Linux operating system to validate real-world performance gains.
• Methodology: FaSe achieves performance gains by only evacuating specific cache lines required for security, rather than the entire cache structure, which is the costly limitation of naive flushing methods.

Implications

• RISC-V Security Enhancement: This work demonstrates the flexibility of the RISC-V ISA by leveraging custom extensions to integrate essential security features (side-channel mitigation) directly into the architecture.
• Secure Computing Viability: FaSe provides a critical, high-performance solution for secure processors, making RISC-V cores like the Rocket Core more viable for sensitive environments where effective side-channel resistance is mandatory.
• Performance/Security Trade-off: By offering significant speed improvements over traditional flushing methods with negligible hardware cost, FaSe dramatically improves the performance/security trade-off in modern processor design.
• Alternative to Partitioning: FaSe provides an efficient alternative to costly or vulnerable countermeasures like cache partitioning and randomization, especially where L1 data cache protection is needed.