FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation

Abstract

FASE (FPGA-Assisted Syscall Emulation) is a novel framework enabling rapid, early-stage processor performance validation by running complex multi-thread benchmarks directly on FPGA-hosted designs, bypassing the need for full SoC integration or a target OS. The framework introduces three key innovations, including a minimal CPU interface and a Host-Target Protocol (HTP), to efficiently delegate Linux-style system calls across the high-latency FPGA-host boundary. FASE achieves high performance validation accuracy (over 91.5% for multi-thread workloads) and efficiency gains exceeding 2000x compared to traditional Proxy Kernels, significantly reducing the processor development lifecycle.

Report

Key Highlights

• Early Validation: FASE enables end-to-end performance validation for new processor designs early in the development process, before completing RTL design and full System-on-Chip (SoC) integration.
• Efficiency Benchmark: It achieves over 2000x higher efficiency compared to using a traditional Proxy Kernel, while introducing less than 1% performance error on single-thread benchmarks (CoreMark).
• High Accuracy: The framework demonstrates high validation accuracy against full SoC validation, reporting over 96% accuracy for most single-thread workloads and over 91.5% accuracy for most complex multi-thread OpenMP workloads.
• Minimal Interface: FASE addresses hardware interface heterogeneity by requiring only a minimal CPU interface to be exposed on the FPGA, leaving other hardware components untouched.
• Open Source: All components of the FASE framework have been released as open-source.

Technical Details

FASE is built around the concept of FPGA-Assisted Syscall Emulation, specifically designed to adapt system call handling for execution directly on FPGA platforms.

• Target Architecture: The validation experiments were conducted utilizing a Xilinx FPGA hosting the open-sourced RISC-V SMP processor, Rocket.
• Benchmarks: Validation used single-thread CoreMark and complex OpenMP multi-thread benchmarks.

Implications

• Accelerated Processor Design: FASE drastically reduces the processor development and iteration cycle (time-to-feedback) by allowing performance validation to begin much earlier, decoupling it from the lengthy SoC integration and OS porting processes.
• Support for Diverse Architectures: This rapid validation capability is crucial for the fast-paced development required by modern AI workloads and the increasing need for domain-specific architectures (DSAs), especially within the competitive RISC-V ecosystem.
• Lowering Development Barrier: By providing a highly efficient, accurate, and open-source platform, FASE lowers the technical barrier for researchers and developers designing new RISC-V microarchitectures, allowing them to focus on core design rather than complex validation infrastructure.
• Standardization of Validation: The high performance and accuracy demonstrated position FASE as a potentially standard, robust method for evaluating processor performance on FPGA prototypes.