Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

Abstract

This paper presents a novel set of non-standard vector instruction types designed to extend the RISC-V ISA for exploring advanced, reconfigurable SIMD operations. The authors introduce a high-performance, open-source RV32 IM softcore optimized for streaming performance and custom SIMD instruction development on FPGAs using HDL templates. By optimizing the cache hierarchy for bandwidth and allowing simultaneous access to multiple operands, this approach facilitates experimentation with advanced custom instructions potentially usable in future reconfigurable CPU architectures.

Report

Key Highlights

• Novel ISA Extension: Introduces new, non-standard vector instruction types specifically for exploring custom SIMD functionality within the RISC-V ISA.
• Operand Efficiency: The new instruction types allow simultaneous access to a relatively high number of operands, which significantly reduces the overall instruction count in applicable workloads.
• Open-Source Softcore: Presents a high-performance, open-source RISC-V (RV32 IM) softcore architecture optimized for custom SIMD instruction exploration and streaming performance.
• Rapid Development: Provides instruction templates in HDL/Verilog, enabling the efficient development of custom, FPGA-based instructions with minimal low-level coding.
• Bandwidth Optimization: The softcore's cache hierarchy is specifically optimized for memory bandwidth, featuring very wide blocks for the last-level cache.

Technical Details

• Core Base: High-performance, open-source RISC-V softcore.
• ISA Base: RV32 IM (Integer and Multiplication/Division).
• SIMD Instruction Design: Focuses on maximizing operand access simultaneously (high number of operands).
• Implementation Platform: FPGA-based softcore implementation.
• Custom Instruction Development: Uses HDL/Verilog instruction templates to simplify hardware definition.
• Cache Hierarchy: Optimized for high bandwidth; features include "very wide blocks" used for the last-level cache.
• Demonstration Focus: Applied to and demonstrated effectiveness on memory-intensive applications.

Implications

• Enabling Customization: Leverages the inherent extensibility of the RISC-V ISA to provide a practical platform for fast prototyping and performance analysis of domain-specific accelerators (SIMD extensions).
• Future Reconfigurable CPUs: The research aims to provide crucial insights into implementing custom, reconfigurable instruction regions in future commercial CPU micro-architectures, pushing the boundaries of CPU flexibility.
• Performance and Density: Reducing instruction count through wide operand access directly improves execution efficiency and instruction density for vectorizable workloads.
• Tooling Advancement: The introduction of HDL templates simplifies the workflow for hardware architects seeking to integrate custom instructions, making the path to specialized core development more accessible.