End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform

Abstract

This paper details an end-to-end Quality of Service (QoS) approach for the SELENE platform, a high-performance RISC-V based heterogeneous SoC targeting safety-related real-time systems. The goal is to provide robust performance guarantees crucial for functional safety in these domains. This is achieved through the cooperative deployment of smart interconnect solutions (buses and NoCs) and specialized multicore interference-aware statistics units.

Report

Key Highlights

• Platform Focus: The research centers on the SELENE platform, an open-source, safety-relevant System-on-Chip (SoC).
• Architectural Base: SELENE utilizes a high-performance, heterogeneous architecture based on the RISC-V Instruction Set Architecture (ISA).
• Domain Target: The platform is specifically designed for safety-related real-time systems, requiring strict performance guarantees.
• Core Innovation: Introduction of an end-to-end Quality of Service (QoS) approach across the entire system to ensure predictable performance.

Technical Details

• QoS Implementation Strategy: The methodology achieves end-to-end QoS cooperatively using specialized hardware components.
• Interconnect Solutions: The system incorporates "smart interconnect solutions" applied to both traditional buses and Networks-on-Chip (NoCs) to manage data flow and latency.
• Interference Mitigation: Specialized multicore interference-aware statistics units are employed to monitor and manage performance degradation caused by shared resource access in multicore environments.
• System Type: The SELENE architecture is described as a heterogeneous SoC, suggesting the integration of various types of processing elements (e.g., CPUs, accelerators).

Implications

• Safety Criticality for RISC-V: This work significantly advances the maturity and viability of open-source RISC-V platforms for use in critical applications (such as automotive, industrial control, or aerospace) where functional safety and hard real-time guarantees are mandatory.
• Addressing Multicore Challenges: By explicitly addressing multicore interference through dedicated statistics units, the platform tackles a major hurdle in ensuring predictable timing behavior, which is essential for certification in safety-related environments.
• Ecosystem Growth: The successful demonstration of end-to-end QoS in an open-source RISC-V platform encourages broader industry adoption and further development within the RISC-V ecosystem for highly regulated markets.