Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP

Abstract

This paper addresses the scarcity of open-source SoC platforms capable of integrating the growing number of open-source RISC-V processors for heterogeneous designs. The authors present modifications to ESP, an open-source SoC platform, specifically enabling multicore execution using the RISC-V CVA6 processor. This modular implementation, based on standardized interfaces, allows RISC-V-based SoCs designed with ESP to successfully boot Linux SMP and execute multithreaded applications on FPGAs, enabling seamless research into heterogeneous, multicore systems.

Report

Key Highlights

• Platform Enhancement: Introduces significant modifications to ESP, an open-source SoC design platform, to support multicore execution.
• RISC-V Integration: Successfully enables the integration and multicore execution of the open-source RISC-V CVA6 processor.
• Linux SMP Support: The modified SoCs are capable of booting Linux Symmetric Multiprocessing (SMP) and running multithreaded applications on FPGAs.
• Modular Design: The implementation utilizes modularity and standardized interfaces, specifically designed to simplify the integration of new, different processor cores.
• Research Focus: Enables the seamless design of a wide array of accelerator-centric, heterogeneous, multicore SoCs for research purposes.

Technical Details

• Base Platform: ESP (open-source SoC design platform).
• Core Utilized: RISC-V CVA6 processor, utilized for multicore setup.
• Architectural Goal: Facilitate the creation of complex heterogeneous systems, combining standardized cores with custom accelerators (building upon ESP's existing accelerator focus).
• Interface Standard: Implementation is based on standardized interfaces to ensure compatibility and ease of integration for other cores.
• Verification Target: Functionality verified on FPGA, including successful booting of Linux SMP.

Implications

• Fills Ecosystem Gap: Addresses a major challenge in the Open Source Hardware (OSH) movement by providing a mature, open-source platform capable of integrating multiple RISC-V cores, which were previously lacking.
• Accelerated Research: Lowers the technical barrier for researchers and developers wishing to experiment with sophisticated heterogeneous, multicore architectures leveraging RISC-V.
• Software Compatibility: By enabling Linux SMP boot, the platform ensures strong software compatibility, allowing researchers to utilize standard operating systems and multithreaded benchmarks immediately.
• Promotes Customization: The modular design ensures that researchers can quickly integrate new or specialized RISC-V cores and custom accelerators into a fully functioning, multicore system.