Electron-Tunnelling-Noise Programmable Random Variate Accelerator for Monte Carlo Sampling

Abstract

This article introduces an electron-tunneling-noise programmable random variate accelerator designed to drastically improve the sampling stage of Monte Carlo simulations. Integrated with a FemtoRV RISC-V soft processor using the LiteX framework on an FPGA, the accelerator achieved an average speedup of 8.70 times compared to the GNU Scientific Library software random number generation. This flexible hardware solution utilizes the FPGA’s hardened XADC block to sample the noise source, offering a highly portable method for accelerating computationally intensive statistical tasks.

Report

Key Highlights

• Novel Accelerator: Development of an Electron-Tunnelling-Noise Programmable Random Variate Accelerator specifically targeting the random sampling stage of Monte Carlo simulations.
• Significant Speedup: Achieves an average speedup of 8.70 times (median 8.68x) across twelve benchmarks compared to standard GNU Scientific Library (GSL) software RNG.
• Computational Bottleneck Relief: The substantial speedup is possible because the target benchmarks spend an average of 90.0% of their execution time generating random samples.
• Distribution Quality: Results obtained using the accelerator exhibit an acceptable quality trade-off, with an average Wasserstein distance of 1.48 times (median 1.41x) that of the GSL baseline.

Technical Details

• Target Processor: FemtoRV imfc RISC-V instruction set soft processor.
• Development Framework: The entire system, including the soft processor and accelerator integration, was generated using the open-source LiteX framework.
• Hardware Platform: Deployed and tested on a Digilent Arty-100T FPGA development board.
• Noise Source Mechanism: The accelerator relies on naturally occurring electron tunneling noise.
• Sampling Hardware: The electron tunneling noise source is sampled using the hardened XADC (Analog-to-Digital Converter) block available within the FPGA.
• Portability: The use of LiteX ensures that the system is highly portable, allowing deployment on any LiteX-supported soft processor and any FPGA board that includes the XADC block.

Implications

• Performance Boost for Statistical Computing: This work provides a crucial hardware acceleration method for tasks dependent on extensive random number generation, such as Monte Carlo methods used in computational physics, risk analysis, and advanced machine learning.
• Validation of Open Hardware Flows: The successful integration and deployment using the open-source LiteX framework and a RISC-V soft core (FemtoRV) demonstrates the maturity and potential of the open hardware ecosystem for developing specialized computing accelerators.
• RISC-V Customization Potential: It highlights how the RISC-V architecture, particularly when paired with FPGA development tools like LiteX, allows researchers to tightly couple physics-based random number generation hardware directly into the processor pipeline, creating efficient application-specific instruction set extensions.
• Emerging Noise Computing: This research validates the utility of utilizing fundamental physical noise sources directly within computing systems to achieve high-throughput, high-quality randomness required for modern simulations.