Elasticlave: An Efficient Memory Model for Enclaves

Abstract

Elasticlave proposes a novel memory model for Trusted Execution Environments (TEEs) that overcomes the severe performance penalties associated with traditional spatial isolation models like Intel SGX. This innovation allows enclaves to selectively and temporarily share memory with the OS and other enclaves, effectively eliminating the need for expensive data copy operations. Prototyped on an RTL-designed RISC-V core, Elasticlave demonstrated performance improvements of one to two orders of magnitude compared to the spatial isolation approach.

Report

Key Highlights

• Performance Improvement: Elasticlave achieves 1 to 2 orders of magnitude performance improvement over the traditional spatial isolation model used by TEEs.
• Memory Sharing: The model enables enclaves to selectively and temporarily share memory regions with other enclaves and the Operating System (OS).
• Eliminates Copies: This sharing capability eliminates the need for expensive data copy operations, which are the primary source of slowdown in conventional TEEs.
• Security Preservation: Elasticlave maintains the same level of application-desired security provided by the strict spatial model.
• Small TCB: The design is noted for having a small Trusted Computing Base (TCB).

Technical Details

• Target Problem: Addresses the performance cost associated with the "spatial isolation model," where enclaves are strictly prevented from sharing memory.
• Implementation Platform: Elasticlave was prototyped on an RTL-designed cycle-level RISC-V core.
• Architecture Scalability: The performance characteristics and hardware area footprint of Elasticlave scale effectively based on the number of shared memory regions configured for support.
• Contrast to SGX: The work explicitly references Intel SGX as an example of a TEE suffering from the performance costs of the spatial isolation model.

Implications

• RISC-V Security Advancement: By integrating an efficient memory model directly on an RTL-designed RISC-V core, Elasticlave provides a high-performance blueprint for TEE implementation within the open-source architecture.
• Enabling Complex Applications: The drastic reduction in overhead (1-2 orders of magnitude) makes TEEs viable for performance-critical applications that require frequent data exchange or complex inter-enclave communication, which were previously impractical due to latency.
• Reduced Trust: Maintaining a small TCB ensures that the hardware mechanisms responsible for security are minimal, which is crucial for easier verification and higher trust in the TEE implementation.