Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6

Abstract

This work presents the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. Integrated into the CVA6 edge architecture, the system was evaluated for its efficiency and hardware cost. The system achieved a remarkable average compression rate of 95.1% compared to full opcode tracing, while introducing only a 9.2% resource utilization overhead on a Xilinx VCU118 FPGA.

Report

Key Highlights

• RISC-V Compliance: The system is designed and evaluated according to the RISC-V Efficient Trace specification, focusing on Instruction Branch Tracing.
• High Compression: Achieved an average data compression rate of 95.1% on platform-specific tests, drastically reducing trace data size compared to tracking full opcode instructions.
• Low Overhead: Implementation introduces a total resource utilization overhead of only 9.2% on the CVA6 subsystem.
• Integration: Successfully integrated into CVA6, a state-of-the-art RISC-V edge architecture.

Technical Details

• Target Specification: RISC-V Efficient Trace (ET) specification for Instruction Branch Tracing.
• Integration Host: CVA6 processor architecture (identified as a state-of-the-art edge architecture).
• Evaluation Platform: Xilinx VCU118 FPGA.
• Compression Metric: 95.1% average compression rate, measured against the baseline of tracing every full opcode instruction.
• Hardware Cost Metric: 9.2% resource utilization overhead.

Implications

• Enhanced Debugging and Verification: Providing a highly efficient, standardized tracing mechanism is vital for verifying and debugging increasingly complex RISC-V cores and SoCs.
• Practical Edge Implementation: The low hardware overhead (9.2%) makes advanced tracing capabilities practical for resource-constrained environments, such as embedded and edge computing systems based on CVA6.
• Ecosystem Maturity: Demonstrating a high-performance implementation (95.1% compression) of the official RISC-V specification accelerates the maturity and industry adoption of the RISC-V tracing infrastructure.
• Reduced Bandwidth Needs: The significant data compression drastically lowers the required bandwidth for transferring trace information off-chip, enabling deeper and longer analyses without needing massive storage solutions.