Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores

Abstract

This paper introduces the COPIFT methodology and associated RISC-V ISA extensions to enable low-cost, flexible dual-issue execution on energy-efficient in-order cores. Designed to accelerate mixed integer and floating-point workloads common in modern general-purpose accelerators, this technique significantly boosts throughput. The implementation demonstrates a 1.47x speedup, reaching a peak of 1.75 instructions per cycle, alongside a 1.37x average energy improvement over optimized RV32G baselines.

Report

Key Highlights

• Focus on Efficiency and Performance: The work targets energy-efficient, area-constrained in-order RISC-V cores used in general-purpose accelerators.
• Dual-Issue Capability: The core innovation is enabling dual-issue execution on traditionally single-issue cores.
• Target Workloads: The methodology is optimized for mixed integer and floating-point instruction sequences, a common characteristic of modern computational tasks.
• Performance Metrics: Achieves substantial acceleration with a 1.47x speedup and a peak instruction per cycle (IPC) of 1.75.
• Energy Efficiency: Reports an impressive 1.37x average energy improvement compared to standard optimized RV32G baselines.

Technical Details

• Methodology: The solution is formalized under the COPIFT methodology.
• Implementation: Dual-issue capability is facilitated through custom RISC-V ISA extensions, implying a minimal hardware overhead design approach.
• Base Architecture: The performance comparison uses optimized RV32G (32-bit integer and floating-point support) baselines, confirming the focus on compact, high-efficiency processors.
• Issue Mechanism: The dual-issue mechanism is specifically designed to handle concurrent execution of disparate instruction types (integer and floating-point) without requiring complex out-of-order execution logic.

Implications

• Bridging the IPC Gap: This work provides a crucial solution for accelerating computation in power-constrained environments, offering performance gains typical of wider-issue designs while maintaining the energy efficiency and simplicity inherent to in-order RISC-V cores.
• RISC-V Ecosystem Enhancement: The introduction of the COPIFT methodology and specific ISA extensions enriches the RISC-V landscape, offering a standardized approach for low-cost, high-efficiency microarchitectural optimization.
• Accelerator Design: The results are highly relevant for designers of specialized accelerators (e.g., AI inference engines, signal processing units) that rely on dense arrays of simple, energy-efficient processing elements (PEs) but require high aggregate throughput.
• Competitive Advantage: By achieving significant performance and energy improvements (1.75 IPC), this development makes energy-efficient in-order RISC-V implementations more competitive against complex, higher-power architectures.