Developing RISC-V Compute Subsystems - Semiconductor Engineering

Abstract

The article addresses the increasing complexity inherent in moving beyond standalone RISC-V core designs to developing fully integrated, high-performance compute subsystems crucial for modern SoCs. It highlights the architectural and methodological challenges concerning verification, security, and IP reuse within heterogeneous computing environments. Successful subsystem development relies on established integration flows and modularity to accelerate time-to-market for specialized, domain-specific RISC-V solutions.

Report

Developing RISC-V Compute Subsystems - Semiconductor Engineering

Key Highlights

• Shift from Core to Subsystem: The industry focus is moving past optimizing individual RISC-V cores toward developing complete, highly integrated compute subsystems necessary for complex SoCs (e.g., AI/ML, automotive).
• Integration Challenges: Key hurdles include managing the increasing number of heterogeneous processing elements, ensuring system-level coherency, and implementing comprehensive verification strategies across the subsystem.
• Modularity and IP Reuse: Emphasizing standardized interfaces and modular design practices is essential to manage complexity, enabling rapid assembly and customization of compute blocks using pre-verified IPs.
• Security and Safety: Security mechanisms (e.g., isolation, secure boot, memory protection) and functional safety requirements (especially for automotive applications) must be integrated at the subsystem level, not merely bolted onto individual cores.

Technical Details

• Coherence Protocols: The architecture requires robust mechanisms (like TileLink or enhanced AXI protocols) to maintain cache coherence across multiple RISC-V cores, accelerators, and shared L2/L3 caches within the subsystem.
• Verification Methodology: Subsystem verification demands advanced techniques, including formal methods and constrained random testing, specifically targeting interactions between processing elements, memory controllers, and I/O devices to prevent complex bugs like deadlocks or data corruption.
• Heterogeneous Interconnect: The use of sophisticated interconnect fabrics is detailed, allowing efficient communication and Quality of Service (QoS) management between different types of compute units (e.g., 64-bit application cores, vector units, specialized hardware accelerators).
• Pipelined Flow: The article likely discusses methodologies for partitioning design and verification tasks, stressing that physical implementation constraints (timing, power, area) must be considered early in the subsystem architectural phase.

Implications

• Market Maturity: The ability to provide robust, pre-verified RISC-V compute subsystems significantly accelerates the maturity of the RISC-V ecosystem, making it a viable alternative to proprietary architectures for mission-critical applications.
• Accelerated Customization: By providing standardized ways to integrate complex components, design teams can rapidly customize their silicon by swapping specialized RISC-V cores or adding domain-specific accelerators, driving innovation in niche markets.
• Reduced Development Risk: Moving complexity from core optimization to subsystem integration helps lower the risk and effort associated with developing new RISC-V based chips, particularly for companies new to designing complex silicon.
• Enhanced Performance Density: Proper subsystem development allows for optimized communication and memory access, leading to better performance per watt compared to integrating loosely connected individual cores.