Design and implementation of a synchronous Hardware Performance Monitor for a RISC-V space-oriented processor

Abstract

This paper details the design and implementation of a synchronous Hardware Performance Monitor (HPM), or Performance Measurement Unit (PMU), integrated into a RISC-V processor intended for space-oriented On-Board Computer (OBC) applications. The core innovation is a novel synchronous monitoring technique where triggered events are propagated through the pipeline to ensure their annotation is precisely synchronized with the executed instruction. This HPM is used to characterize the processor’s execution model and is validated through safety-critical benchmarks, including CoreMark and Dhrystone.

Report

Key Highlights

• Target Application: The HPM is designed for a RISC-V On-Board Computer (OBC) tailored specifically for safety-critical space applications.
• Crucial Function: The capability to collect execution statistics (timing performance and resource utilization) is deemed mandatory for verifying safety-critical software systems.
• Novel Synchronization: The monitoring technique employs a synchronous approach, ensuring event counts are not immediate but are perfectly aligned with the instruction that triggered them by propagating the event signal through the pipeline.
• Validation: The PMU was utilized to successfully characterize the execution model of the processor and demonstrated its statistical capabilities using standard industry benchmarks, CoreMark and Dhrystone.

Technical Details

• Component: Performance Measurement Unit (PMU), also known as Hardware Performance Monitor (HPM).
• Integration: Integrated directly into the RISC-V CPU pipeline architecture.
• Measurement Target: Measures statistics related to program execution, timing performance, and resource utilization.
• Methodology: Implementation of a synchronous monitoring technique that delays the counting of triggered events until the corresponding instruction reaches the appropriate pipeline stage, thereby ensuring high measurement accuracy.

Implications

• Enhanced Safety and Verification: Providing precise, synchronous performance statistics is vital for safety-critical domains like aerospace, allowing mandatory analysis of software timing requirements and extra-functional properties.
• Improved Execution Characterization: The PMU enables detailed characterization of the processor's execution model, which is essential for optimizing software and predicting performance in constrained environments.
• Advancing RISC-V in Space: This work demonstrates the growing maturity and adaptability of the RISC-V architecture for highly specialized, high-reliability applications such as OBCs, furthering its adoption in the space sector.
• Measurement Fidelity: The synchronous approach addresses inherent measurement inaccuracies common in traditional performance monitors, offering higher fidelity data required for rigorous certification processes.