Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing

Abstract

This paper analyzes the performance of a custom RISC-V SoC implementation, utilizing the RV32I base ISA with M and A extensions, specifically targeting edge computing applications. Through cycle-accurate simulation, the pipelined design achieved substantial power efficiency gains, demonstrating a 17% reduction in power consumption compared to equivalent ARM Cortex-M0 implementations. The research validates RISC-V's open architecture and scalability for integrating custom DSP accelerators, proving its strength for embedded and domain-specific systems.

Report

Key Highlights

• The research focuses on the design and implementation of a RISC-V System-on-Chip (SoC) specifically tailored for edge computing and custom Digital Signal Processing (DSP) acceleration.
• The core implementation demonstrated a significant 17% reduction in power consumption when benchmarked against standard ARM Cortex-M0 implementations in comparable process nodes.
• Performance evaluation was conducted using cycle-accurate simulation to measure metrics like CPI (cycles per instruction) and power efficiency.
• The study underscores RISC-V's modularity, validating its capability for custom domain-specific optimizations and scalability for accelerators.

Technical Details

• Base ISA: RISC-V RV32I (32-bit Integer base instruction set).
• Extensions Examined: M (Multiplication and division) and A (Atomic operations).
• Implementation Type: Pipelined implementation.
• Evaluation Method: Cycle-accurate simulation.
• Measured Metrics: CPI and power efficiency.
• Comparative Data: Performance results were compared directly against the ARM Cortex-M0 core.
• Target Application Space: Embedded systems and edge computing requiring custom DSP acceleration.

Implications

• Market Viability: The demonstrated 17% power advantage over the industry-standard ARM Cortex-M0 provides a strong technical argument for RISC-V adoption in highly power-constrained microcontroller and embedded systems markets.
• Accelerator Customization: The successful integration approach, coupled with the open-standard nature of RISC-V, validates its utility for rapidly developing domain-specific architectures, which is crucial for modern AI and signal processing workloads at the edge.
• Ecosystem Confidence: The research provides concrete performance data supporting RISC-V’s claim to superiority in embedded power efficiency, encouraging broader industry investment and design adoption within the growing RISC-V hardware ecosystem.