DAC 61: EDA addressing growing system complexity - embedded.com

Abstract

The 61st Design Automation Conference (DAC 61) centered on how Electronic Design Automation (EDA) tools are evolving to tackle the exponentially growing complexity of modern electronic systems. Innovations focused heavily on managing challenges inherent in heterogeneous integration, advanced process nodes, and the design of massive AI/ML accelerators. This shift underscores the necessity for comprehensive, system-level design methodologies to enable the next generation of computing architectures.

Report

Report: DAC 61: EDA Addressing Growing System Complexity

Key Highlights

• System-Level Focus: EDA vendors showcased a critical pivot from traditional block-level optimization to comprehensive, system-level design and integration solutions necessary for large, multi-die SoCs.
• Heterogeneous Integration: A significant focus was placed on tools supporting 3D ICs and chiplet architectures, addressing challenges in physical design, thermal management, and inter-die verification.
• AI/ML Acceleration: New EDA flows were introduced specifically tailored for high-performance computing (HPC) and massive data movement in AI accelerators, utilizing advanced process nodes (e.g., sub-5nm).
• Reliability and Verification: The conference emphasized enhanced formal verification techniques and tools to ensure system integrity and reliability at advanced nodes, where variability and aging effects are increasingly problematic.
• Digital Transformation in Design: The rising adoption of digital twins and virtual prototyping tools was highlighted, enabling earlier software development and system analysis before silicon tape-out.

Technical Details

• Advanced Node Support: EDA suites demonstrated improved capabilities for managing extreme complexity at 3nm and 2nm nodes, specifically concerning layout optimization, lithography modeling (e.g., DFM), and electromigration analysis.
• 3D IC Co-Design: Tools supporting Unified Chiplet Interconnect Express (UCIe) standardization were prominent, facilitating the co-optimization of packaging, interposer routing, and logic placement in vertically integrated stacks.
• ML-Enhanced EDA: Machine Learning algorithms are increasingly integrated into traditional EDA tasks, such as placement, routing, and timing closure, to rapidly explore massive design spaces and achieve better PPA (Power, Performance, Area) targets.
• Verification Through Formal Methods: Advancements in formal verification are necessary to handle the combinatorial explosion of states in highly integrated systems, focusing on efficient assertion-based verification and automated test generation.

Implications

• Accelerating RISC-V Customization: Improved EDA flows significantly lower the design complexity and time-to-market barrier for companies designing specialized, custom RISC-V cores and accelerators, maximizing the inherent flexibility of the open ISA.
• Enabling Chiplet Ecosystem: Robust EDA support for 3D ICs and chiplets is foundational for the RISC-V ecosystem, allowing different IP vendors (e.g., custom accelerators, I/O blocks, standard compute tiles) to be integrated efficiently into competitive heterogeneous products.
• Competitive PPA for HPC: By leveraging ML-driven EDA and advanced node optimization, RISC-V designs can achieve highly optimized Power, Performance, and Area figures, making them viable competitors in performance-intensive markets like data centers and automotive.
• Faster Innovation Cycle: Enhanced system-level modeling and verification allow RISC-V implementers to prototype and validate system architectures more quickly, driving rapid iteration and innovation in processor design.