d-Matrix and Andes Collaborate on RISC-V Accelerator for AI Inference - insidehpc.com

Abstract

d-Matrix and Andes Technology have announced a strategic collaboration to develop a high-efficiency AI inference accelerator leveraging the open-standard RISC-V instruction set architecture. This partnership combines d-Matrix's specialized AI hardware design capabilities with Andes' extensive portfolio of robust RISC-V CPU intellectual property (IP). The resulting accelerator aims to provide a competitive, power-efficient solution for demanding AI workloads, driving RISC-V adoption in data center and edge computing markets.

Report

d-Matrix and Andes Collaborate on RISC-V Accelerator for AI Inference

Key Highlights

• Strategic Partnership: The collaboration links d-Matrix, a specialist in AI computing solutions, with Andes Technology, a leading provider of RISC-V processor IP.
• Target Application: The joint effort focuses specifically on developing hardware accelerators optimized for AI Inference tasks.
• Architecture Standard: The solution is fundamentally built upon the open and extensible RISC-V Instruction Set Architecture (ISA).
• Goal: The initiative aims to deliver a high-performance, energy-efficient solution to meet the rapidly growing demand for specialized AI hardware.

Technical Details

• Core Technology Integration: The solution involves integrating d-Matrix's specialized AI computation engines (likely featuring advanced matrix multiplication or dataflow units) with Andes' commercial RISC-V CPU cores.
• Role of RISC-V: The Andes RISC-V cores will likely serve as the control plane for the accelerator, handling task scheduling, operating system interaction, and managing the flow of data to the specialized AI processing units.
• Performance Metric Focus: The architecture is designed to maximize key metrics such as inferences per second per watt, crucial for scalable data center deployments.
• Open Standard Foundation: Utilizing RISC-V ensures that the resulting product benefits from the flexibility and growing toolchain support inherent in an open ISA.

Implications

• Validation of RISC-V for HPC/AI: This partnership provides significant validation for RISC-V's suitability not just for embedded systems, but for high-performance, complex workloads like AI acceleration, directly challenging proprietary architectures.
• Market Diversification and Competition: The collaboration introduces a serious, open-standard competitor into the tightly controlled AI accelerator market (currently dominated by companies like NVIDIA and Intel), fostering greater innovation and vendor choice.
• Ecosystem Maturity: The development of a highly integrated AI accelerator necessitates significant improvements and expansion in the RISC-V software ecosystem, including compiler support, toolchains, and AI framework integration (e.g., compatibility with TensorFlow and PyTorch).
• Supply Chain Resilience: Leveraging an open standard like RISC-V offers opportunities for greater supply chain transparency and customization, reducing reliance on single-source CPU IP providers.