Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem

Abstract

This paper presents a cycle-accurate evaluation framework for software-hardware co-design solutions targeting decimal computation within the RISC-V ecosystem. The methodology involves integrating dedicated hardware, realized as an accelerator supporting new decimal-oriented instructions, into the system design. This approach provides precise analysis of both performance and hardware overhead, enabling developers to find optimal Pareto points compared to traditional estimation methods.

Report

Key Highlights

• Focus Area: Software-hardware co-design specifically for complex decimal computation.
• Target Platform: Evaluation is performed within the RISC-V ecosystem.
• Evaluation Standard: Introduction of a framework capable of cycle-accurate analysis for both performance and hardware cost.
• Optimization Goal: Identifying optimal Pareto points (trade-offs between hardware cost and computational performance) for embedded systems development.
• Validation: Performance results obtained via the cycle-accurate framework are compared against estimations using dummy functions.

Technical Details

• Architecture: Software-Hardware Co-Design approach, where complex logic is partitioned between software routines and specialized hardware.
• Hardware Implementation: The dedicated hardware component is structured as an accelerator.
• Instruction Set Extension: The framework utilizes and evaluates the performance of newly developed decimal oriented instructions integrated into the RISC-V system and supported by the accelerator.
• Metrics: The primary evaluation involves measuring cycle count (performance) and assessing hardware overhead (cost).

Implications

• RISC-V Specialization: This work advances the maturity of the RISC-V ecosystem by providing precise methods for integrating and evaluating specialized arithmetic functions (like decimal computation, critical for commercial and financial applications).
• Accurate Design Methodology: By offering cycle-accurate results rather than simple dummy function estimations, the framework allows designers to make significantly more informed decisions about co-design trade-offs.
• Hardware Extension Standard: The methodology provides a template for how new, custom instruction set extensions—particularly those backed by dedicated accelerators—can be rigorously evaluated for inclusion in RISC-V based systems.
• Embedded Systems Optimization: The ability to precisely map Pareto points ensures that high-performance, cost-effective embedded systems requiring decimal precision can be designed efficiently.