CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor

Abstract

CVA6-VMRT proposes a modular hardware extension for the open-source RISC-V CVA6 core to achieve time-predictable virtual memory, addressing a critical need in complex autonomous systems. This design incorporates dynamically partitioned Translation Look-aside Buffers (TLBs) and hybrid L1 cache/scratchpad memory (SPM) functionality, allowing the operating system to ensure single-cycle address translation for critical tasks. This approach enhances execution time determinism by 94% during interference from non-critical guests while incurring only a 4% area overhead.

Report

Key Highlights

• Core Innovation: CVA6-VMRT is a hardware extension to the 64-bit application-class RISC-V CVA6 processor designed to introduce time-predictable virtual memory access.
• Target Domain: Focuses on integrated heterogeneous SoCs requiring deterministic Worst-Case Execution Times (WCETs) and low latency for real-time and safety-critical autonomous systems.
• Performance Gain: The system enhances execution time determinism for critical guests by 94% when operating under interference from non-critical guests.
• Efficiency: Achieves this significant improvement with minimal overhead—only a 4% area increase and no timing penalty compared to the baseline CVA6 core.

Technical Details

• Baseline Architecture: The work extends the open-source RISC-V CVA6 core.
• TLB Mechanism: Features dynamically partitioned Translation Look-aside Buffers (TLBs) to minimize interference across tasks.
• Predictable Translation: The hardware provides fine-grained, per-thread control, allowing the Operating System (OS) to manage TLB replacements, including static overwrites. This guarantees single-cycle address translation for time-critical memory regions.
• Cache Management: Supports hybrid L1 cache/scratchpad memory (SPM) functionality. The system enables runtime partitioning of both instruction and data caches into standard cache sections and high-predictability SPM sections.
• Addressing Limitations: The approach is proposed as a superior alternative to existing techniques like software coloring or memory replication, which often introduce substantial area and performance overheads.

Implications

• Enabling Real-Time RISC-V: This work significantly increases the viability of 64-bit RISC-V cores in hard real-time and safety-critical markets (e.g., automotive, aerospace) where strict WCET guarantees are essential.
• Modular Predictability: By integrating predictability features as a modular extension, CVA6-VMRT offers a blueprint for how open-source core development can address complex non-functional requirements (like determinism) efficiently.
• Virtualization Enhancement: The 94% improvement in determinism during guest interference highlights its importance for robust virtualization environments, ensuring that critical virtual machines maintain performance guarantees even under heavy load from untrusted or non-critical guests.
• Low Cost Solution: Achieving substantial determinism improvements with only a 4% area overhead makes CVA6-VMRT a highly attractive, cost-effective solution compared to traditional resource isolation methodologies.