ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package

Abstract

ControlPULPlet is an open-source, real-time multi-core RISC-V controller designed specifically to manage coupled operation within 2.5D Systems-in-Package (SiP). The architecture minimizes performance penalties from die-to-die communication by integrating a 32-bit CV32RT core, a specialized DMA engine, and an acceleration cluster connected via an efficient AXI4-compatible D2D link. Fabricated as the Kairos demonstrator in TSMC 65nm, the system runs Model Predictive Control up to 290 MHz and achieves a high-speed peak duplex transfer rate of 51 Gbit/s with minimal area overhead.

Report

Key Highlights

• Innovation: ControlPULPlet is an open-source, real-time multi-core RISC-V controller optimized for 2.5D Systems-in-Package (SiP) integration.
• Core Challenge Addressed: Minimizing the performance penalty associated with die-to-die (D2D) communication crucial for real-time control in SiPs.
• Performance Metrics: The silicon demonstrator, Kairos, operates at up to 290 MHz while maintaining a low 30 mW power envelope running complex Model Predictive Control algorithms.
• Communication Efficiency: The flexible D2D link achieves a peak duplex transfer rate of 51 Gbit/s at 200 MHz.
• Area Efficiency: The physical layer (PHY) area cost of the D2D link is exceptionally low, requiring just 7.6 kGE per channel and contributing only 2.9% to the total system area.

Technical Details

• Primary Core: Features a 32-bit CV32RT core, specifically chosen for its fast interrupt handling capabilities required for real-time operation.
• Data Flow Automation: Includes a specialized Direct Memory Access (DMA) engine dedicated to automating periodic sensor readout, reducing CPU overhead.
• Acceleration Cluster: Integrates a tightly-coupled programmable multi-core cluster for accelerating advanced control algorithms, connected via a dedicated AXI4 port.
• Inter-Die Communication Standard: Utilizes a flexible AXI4-compatible D2D link to ensure efficient and standardized communication across the 2.5D SiP.
• Fabrication and Power: Implemented and fabricated in TSMC's 65nm CMOS process technology.

Implications

• Enabling 2.5D Architectures: This design provides a validated, high-performance controller solution essential for managing the tightly coupled and highly demanding operational requirements of next-generation 2.5D SiP architectures.
• RISC-V Ecosystem Growth: By leveraging open-source components and the CV32RT core, ControlPULPlet reinforces the use of RISC-V in high-stakes, real-time control applications, proving the architecture's suitability against stringent latency and power constraints.
• Chiplet Design Methodology: The successful implementation of a high-bandwidth (51 Gbit/s) D2D link with minimal area overhead validates cost-effective methods for inter-chiplet communication, lowering the barrier for adopting chiplet-based heterogeneous integration.
• Open Source Contribution: ControlPULPlet’s open-source nature promotes wider adoption, modification, and innovation within the hardware architecture community developing complex heterogeneous systems.