CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses

Abstract

CodeAPeel is a novel, multi-layered learning technology for computer architecture courses that simulates instruction processing across compiler, assembly, and machine layers. Unlike simulators modeling real processors (e.g., RISC-V), CodeAPeel utilizes a generic RISC Instruction Set Architecture (ISA). Crucially, it provides a dual-mode SISD/SIMD processor simulation, featuring advanced, built-in vector instruction support for visualizing complex parallel operations.

Report

Structured Report: CodeAPeel

Key Highlights

• Layered Learning Technology: CodeAPeel is designed as a versatile, multi-layered system supporting the teaching and learning of core computer architecture concepts.
• Generic RISC Simulator: It simulates a generic RISC instruction set architecture (ISA), intentionally avoiding the simulation of specific, real-world processors like MIPS or RISC-V.
• Dual-Mode Processing: The simulator supports both scalar (SISD) and vector (SIMD) instruction execution modes, aligning with Flynn's classification.
• Comprehensive Visualization: The tool provides detailed animation of instruction processing across compiler, assembly, and machine layers.

Technical Details

• Simulation Scope: Performs a comprehensive simulation of the CPU's fetch-decode-execute cycle.
• Visualization Components: Animates the behavior of crucial architectural components, including CPU registers, RAM, VRAM, STACK memories, various control registers, and the graphics screen.
• Instruction Repertoire: The generic ISA includes both scalar and vector instructions.
• Vectorization: Vectorization capabilities are explicitly built into the instruction repertoire to facilitate the simulation of processors supporting powerful vector operations.

Implications

• Enhanced Foundational Understanding: By focusing on a generic RISC ISA rather than a specific complex implementation like RISC-V, CodeAPeel allows students to grasp fundamental architectural principles without being distracted by specific commercial or historical ISA quirks.
• Preparation for Modern Architecture: The built-in support for SIMD and vector instructions addresses a key aspect of modern high-performance computing and parallelism, which is highly relevant to extensions like the RISC-V Vector Extension (V).
• Supporting the Tech Ecosystem: CodeAPeel provides a robust educational tool for future engineers, ensuring they have a conceptual foundation in instruction processing and dual-mode operation before tackling the specifics of emerging architectures like RISC-V, thereby strengthening the quality of new talent entering the hardware architecture field.