Co-emulation platform targets complex RISC-V chip design - Engineering.com

Abstract

A newly introduced co-emulation platform is specifically engineered to handle the high complexity and customizability inherent in advanced RISC-V chip designs. This verification solution integrates high-speed hardware emulation with software simulation, enabling designers to efficiently test customized instruction set extensions and multi-core architectures. The platform aims to accelerate the debugging cycle and ensure functional correctness for complex System-on-Chips, thereby speeding up time-to-market.

Report

Key Highlights

• Targeted Verification: The platform is specifically designed to address the unique challenges of complex RISC-V architecture implementation, including highly customized cores and accelerators.
• Co-emulation Methodology: It utilizes co-emulation, blending the high fidelity of hardware emulation (typically using FPGAs or specialized emulation boxes) with the flexibility and speed of software instruction set simulation (ISS).
• Handling Complexity: The main objective is managing the verification complexity introduced by RISC-V's extensibility, particularly in heterogeneous computing environments.
• Accelerated Development: The solution enables design teams to 'shift left,' allowing software development and hardware/software integration testing to begin much earlier in the design cycle.

Technical Details

• Integration: The core technical achievement is the seamless integration environment, allowing real-world stimuli and large-scale test cases to run across the partitioned hardware/software models.
• Architectural Support: The platform must support multiple RISC-V processor configurations (e.g., RV32I, RV64G, custom extensions) and heterogeneous core clusters within the SoC.
• Verification Speed: Co-emulation is typically leveraged to run verification steps at near-real-time speeds (MHz range), significantly faster than pure simulation (KHz range), essential for running full operating system boots and complex application workloads.
• Debug Capabilities: Includes advanced debug features that allow designers to seamlessly probe and analyze signals across both the hardware (emulated) and software (virtual platform) domains simultaneously.

Implications

• Maturity of Ecosystem: The introduction of specialized, high-performance verification tools signifies the increasing maturity and commercial readiness of the overall RISC-V ecosystem.
• Encouraging Customization: By providing a robust way to verify complex designs, the platform reduces the risk associated with developing proprietary RISC-V extensions, fostering further innovation.
• Competition: This offering places RISC-V verification capabilities closer to parity with established proprietary architectures, making the development path for advanced SoCs more predictable and reliable.
• Wider Adoption: It lowers the barrier to entry for large semiconductor companies building mission-critical or highly specialized devices based on RISC-V, which require rigorous, production-grade verification methodologies.