CIDPro: Custom Instructions for Dynamic Program Diversification

Abstract

CIDPro is a novel framework that uses dynamic program diversification and custom instruction generation to mitigate timing side-channel attacks in embedded systems. It integrates the LLVM compiler and the RISC-V FPGA soft-processor, where the compiler automatically generates custom instructions for security-critical code segments. Implemented on the Zynq7000 FPGA, CIDPro achieved an 80% to 86% reduction in timing side-channel capacity with only a negligible 1% hardware area overhead.

Report

Key Highlights

• Security Mitigation: CIDPro directly addresses timing side-channel attacks, a significant security threat to embedded systems.
• Core Mechanism: It employs Dynamic Program Diversification (DPD) realized through the automatic generation and execution of custom instructions.
• Platform Integration: The framework integrates the widely used LLVM compiler infrastructure with the flexible RISC-V FPGA soft-processor architecture.
• Proven Effectiveness: Experimental results demonstrate a substantial security gain, achieving 80% and 86% timing side-channel capacity reduction for two benchmarks.
• Efficiency: The method maintains low hardware overhead, utilizing only 1% of the total RISC-V system slices on the FPGA.

Technical Details

• Architecture: CIDPro connects the software compilation stack (LLVM) with the hardware platform (RISC-V custom co-processor).
• Compiler Role: The LLVM compiler is responsible for automatically identifying security-critical code sections and generating corresponding custom instructions.
• Hardware Implementation: The custom instructions execute on a dedicated RISC-V custom co-processor block, which is engineered to introduce diversified timing characteristics upon each execution instance.
• Evaluation Device: Implementation and testing were conducted on the Zynq7000 XC7Z020 FPGA device.

Implications

• RISC-V Ecosystem Advancement: CIDPro demonstrates a practical and high-impact application of the RISC-V ISA's extensibility feature, showing how custom instructions can be leveraged for sophisticated security defenses.
• Enhanced Embedded Security: By providing an automated, compiler-supported method to combat side-channel leakage, this framework makes RISC-V-based embedded systems much more viable for security-sensitive domains like IoT and cryptography.
• Automated Hardening: Integrating this defense mechanism directly into the LLVM toolchain allows developers to automatically harden software without manual, error-prone hardware modifications, accelerating secure system development.
• Favorable Tradeoffs: The solution validates that strong security guarantees (up to 86% capacity reduction) can be achieved using dynamic diversification with highly efficient resource utilization (1% area overhead), making it suitable for constrained FPGA environments.