Chip designer SiFive aims to cram more RISC-V cores into AI chips - theregister.com

Abstract

Chip designer SiFive is strategically focusing its intellectual property (IP) development on high-performance artificial intelligence (AI) accelerators by aiming to significantly increase the density of RISC-V cores. This initiative seeks to leverage the flexibility of the RISC-V architecture to create specialized, scalable multi-core clusters optimized for the massive parallel processing demands of modern AI workloads. The aggressive density push positions SiFive to become a key supplier for next-generation neural processing units and custom AI silicon.

Report

SiFive's Strategy: High-Density RISC-V for AI

SiFive is shifting its design priorities to address the exploding demand for specialized AI hardware, emphasizing core density as a competitive advantage.

Key Highlights

• Strategic Focus: SiFive, a leading commercial RISC-V IP vendor, is pivoting heavily toward AI and machine learning applications.
• Core Density: The primary innovation involves designing architectures capable of integrating a significantly higher number of RISC-V cores onto a single piece of silicon compared to traditional CPU designs.
• Target Market: The IP is tailored specifically for use in AI chips, neural processing units (NPUs), and specialized accelerators requiring immense parallel computing power.
• Competitive Edge: This approach leverages RISC-V's inherent modularity and efficiency to offer a highly scalable and power-efficient alternative to proprietary architectures in the AI space.

Technical Details

While specific core counts or product names are inferred, the technical thrust revolves around:

• Multi-Core Clusters: Designing optimized RISC-V clusters (potentially utilizing the RISC-V Vector Extension, RVV) that function effectively as cohesive processing units for matrix multiplication and tensor operations.
• Interconnect Optimization: Implementation of highly efficient, low-latency interconnects (such as cache coherence fabrics) necessary to manage data flow and communication across hundreds or thousands of closely integrated cores.
• Specialization: Focusing on smaller, highly parallel RISC-V microarchitectures that prioritize density and efficiency over maximum single-thread performance, a characteristic ideal for AI training and inference.

Implications

• Validation of RISC-V: This move solidifies RISC-V's transition from an embedded/control CPU architecture to a viable, high-performance solution capable of challenging established proprietary IP in demanding, cutting-edge markets like AI.
• Accelerated Customization: SiFive’s ability to offer high-density RISC-V IP enables AI chip designers (especially hyper-scalers and semiconductor startups) to rapidly create custom silicon perfectly tailored to their specific AI models, avoiding the lock-in associated with fixed architectures.
• Increased Competition: By providing a scalable, open-source-based solution, SiFive intensifies competition with major players like Nvidia, AMD, and ARM in the high-growth sector of AI acceleration hardware, driving down costs and fostering greater innovation.