Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Abstract

Cheshire is a lightweight, Linux-capable 64-bit RISC-V host platform designed to facilitate the seamless integration of domain-specific accelerators, targeting energy-constrained IoT and TinyML applications. Its core architectural features include a unique low-pin-count DRAM interface (RPC DRAM), a last-level cache configurable as scratchpad memory, and an efficient DMA engine for data movement. Implemented as the Neo silicon demonstrator in TSMC 65nm technology, the platform operates up to 325 MHz while maintaining total power consumption under 300 mW and is available as free and open-source synthesizable RTL.

Report

Key Highlights

• Open-Source Host Platform: Cheshire is a lightweight, 64-bit RISC-V host platform available as free and open-source synthesizable RTL, supporting widespread adoption and customization.
• Linux-Capable: The platform is robust enough to run Linux, enabling high-level coordination and OS support for complex heterogeneous architectures.
• Target Domain: Specifically designed for extreme-edge IoT and TinyML domains where power and cost constraints are critical, requiring the use of specialized multicore accelerators.
• Low-Pin-Count DRAM: Features a unique RPC DRAM interface optimized for high energy efficiency and minimal area consumption.
• Silicon Demonstrator: Cheshire was implemented and fabricated as a silicon demonstrator named "Neo" in TSMC's 65nm CMOS technology.

Technical Details

• Core Architecture: 64-bit RISC-V host processor designed to coordinate compute-specialized accelerators.
• Memory System: Includes a last-level cache (LLC) that is configurable to operate as scratchpad memory, facilitating fast, dedicated memory access for accelerators.
• Data Transport: Utilizes a high-efficiency Direct Memory Access (DMA) engine for moving data between DRAM and accelerators.
• Performance (Neo): Achieves clock frequencies up to 325 MHz at 1.2 V and limits total power consumption to under 300 mW during data-intensive workloads.
• RPC DRAM Metrics: The low-pin-count DRAM interface consumes only 250 pJ/B of energy and requires a physical layer (PHY) area of just 3.5 kGE (gate equivalent).
• Transfer Rate: The RPC DRAM interface attains a peak transfer rate of 750 MB/s when clocked at 200 MHz.
• Peripherals: Provides standard optional I/O interfaces, including UART, SPI, I2C, VGA, and GPIOs.

Implications

• Enabling Heterogeneous Edge Computing: Cheshire significantly lowers the barrier for researchers and companies to build advanced heterogeneous systems by providing a stable, Linux-capable, and lightweight host environment ready for custom RISC-V accelerator plug-in.
• Optimization for IoT/TinyML: The platform's strong focus on power efficiency (sub-300 mW operation) and the innovative energy-saving RPC DRAM interface directly addresses the most severe constraints in extreme-edge computing.
• Advancing RISC-V Open Hardware: By releasing the full synthesizable RTL, the Cheshire project contributes substantial, high-quality IP to the open-source RISC-V ecosystem, accelerating modular development and architectural innovation in embedded systems.