ChatArch: A Knowledge-driven Graph-of-thought LLM Framework for Processor Architecture Optimization

Abstract

ChatArch introduces a novel Knowledge-driven Graph-of-thought (GoT) LLM framework designed to automate and optimize the challenging process of processor architecture design. By integrating domain-specific knowledge graphs, ChatArch facilitates structured, multi-path reasoning for evaluating complex architectural trade-offs, surpassing the limitations of sequential LLM chains. This approach significantly accelerates design space exploration, leading to the rapid identification of more efficient and highly specialized processor configurations.

Report

Key Highlights

• Novel Framework: Introduction of ChatArch, an end-to-end framework leveraging Large Language Models (LLMs) for complex processor architecture optimization.
• Graph-of-Thought (GoT) Reasoning: Moves beyond traditional sequential Chain-of-Thought reasoning by structuring architectural dependencies and trade-offs into a graph, enabling more robust, non-linear evaluation of design choices.
• Knowledge-Driven Approach: The framework is grounded by expert architectural knowledge (e.g., ISA specifications, historical performance metrics, design constraints), mitigating LLM hallucinations and ensuring physically realizable designs.
• Automation of HDS: Automates critical steps in Hardware Design Space (HDS) exploration, drastically reducing the manual effort required to analyze the massive parameter space of modern processors.

Technical Details

• Framework Architecture: ChatArch utilizes a specialized LLM (likely fine-tuned on architecture benchmarks and design documents) coupled with a dynamic graph database representing the design space.
• GoT Implementation: The Graph-of-Thought mechanism models microarchitectural parameters (e.g., cache size, pipeline depth, branch prediction algorithms) as nodes, with edges representing dependencies and performance/power trade-offs.
• Optimization Targets: The primary optimization target involves maximizing performance (e.g., IPC) while adhering to strict constraints on power consumption, area (PPA), and latency.
• Design Space: The framework is explicitly geared toward processor optimization, suggesting applicability to complex, configurable architectures such as those based on the RISC-V Instruction Set Architecture (ISA).
• Workflow: The process likely involves: (1) Knowledge Graph initialization, (2) LLM generating initial design proposals, (3) GoT structured evaluation and refinement, and (4) interfacing with established EDA simulation tools for verification.

Implications

• Advancing RISC-V Customization: For the RISC-V ecosystem, which thrives on modularity and custom instruction extensions, ChatArch provides a powerful tool to explore the exponentially large configuration space quickly, democratizing the creation of highly specialized domain-specific accelerators.
• Shift in EDA Paradigm: Represents a significant move in Electronic Design Automation (EDA) from purely algorithmic optimization and extensive manual simulation toward AI-driven, high-level architectural synthesis and verification.
• Accelerated Time-to-Market: By automating complex architecture evaluation cycles, ChatArch drastically reduces the overall development time required for new processor generations and domain-specific hardware.
• Handling Architectural Complexity: The GoT methodology enables designers to manage the overwhelming complexity of modern heterogeneous systems, ensuring that optimizations across disparate microarchitectural blocks are harmonized effectively.