Abstract

This paper presents a comprehensive, open-source ecosystem centered on Coarse-Grained Reconfigurable Architectures (CGRAs) to enable agile hardware-software co-design for AI and edge computing workloads. Key contributions include HyCUBE, a novel CGRA with a reconfigurable single-cycle multi-hop interconnect, and PACE, a RISC-V SoC integrating the HyCUBE accelerator for power efficiency. The entire platform is supported by Morpher, an architecture-adaptive design framework that facilitates end-to-end design space exploration and validation, ultimately advocating for a unified abstraction layer for all spatial accelerators.

Report

Building an Open CGRA Ecosystem for Agile Innovation

Key Highlights

• Goal: Address the demanding performance and energy targets of modern AI and edge workloads through open, agile hardware-software co-design.
• Technology Focus: Coarse-Grained Reconfigurable Architectures (CGRAs) are utilized for their balance of flexibility and efficiency.
• Ecosystem Components: The authors introduce a fully open-source CGRA ecosystem consisting of the HyCUBE hardware accelerator, the PACE SoC integration, and the Morpher design framework.
• Openness Philosophy: The platform utilizes open-source hardware generators and software toolchains to lower innovation barriers and promote reproducible research.
• Future Vision: The paper concludes with a call for a unified abstraction layer for CGRAs and spatial accelerators to decouple hardware specialization from software development.

Technical Details

• HyCUBE: This is the core CGRA architecture featuring a crucial innovation: a reconfigurable single-cycle multi-hop interconnect. This design is intended to facilitate highly efficient data movement across the accelerator structure.
• PACE: This is a specific implementation where the power-efficient HyCUBE CGRA is embedded within a RISC-V System-on-Chip (SoC). This integration targets high-performance, low-power edge computing applications.
• Morpher: Morpher is described as the fully open-source, architecture-adaptive design framework. It provides comprehensive support for critical steps in CGRA development, including design space exploration, compilation, simulation, and validation.
• Architecture Adaptation: The ecosystem supports cross-layer optimization, allowing the architecture to be tailored and validated using the Morpher framework.

Implications

• Acceleration of Innovation: By providing a complete, open-source stack (from hardware generation to software toolchain), the ecosystem significantly lowers the barrier to entry for researchers and developers working on custom accelerators.
• Strengthening the RISC-V Ecosystem: Embedding the HyCUBE accelerator within a RISC-V SoC (PACE) showcases the versatility of RISC-V as a robust platform for integrating specialized, open-source hardware, deepening its utility in the edge AI space.
• Standardization Potential: The proposal for a unified abstraction layer for CGRAs and spatial accelerators is critical. If adopted, this standard could drive architectural portability and compiler innovation, ensuring that optimized software stacks are not tied exclusively to proprietary hardware.
• Reproducibility and Trust: The emphasis on openness at every layer ensures that research results are verifiable and reproducible, benefiting the academic and industrial hardware architecture community.