BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox

Abstract

BRISC-V is an open-source, parameterized, and synthesizable register-transfer level (RTL) platform designed for comprehensive architecture design space exploration of RISC-V systems. It provides highly modular components spanning simple single-core designs to complex multi-core Systems-on-Chip (SoCs) incorporating memory hierarchies and Networks-on-Chip (NoC). The platform facilitates rapid prototyping and targeted architectural modifications, supporting both RTL simulation and vendor-agnostic FPGA emulation, and includes a RISC-V compiler toolchain and web-based configuration tools.

Report

BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox

Key Highlights

• Open-Source RTL Platform: BRISC-V is an open-source platform specifically designed for Register-Transfer Level (RTL) architecture design space exploration (DSE).
• Parameterized & Synthesizable: The platform uses a parameterized set of synthesizable RTL modules (implemented in standard Verilog) suitable for creating various RISC-V based single and multi-core systems.
• High Modularity: Components are designed to be composable and highly modular, allowing for targeted, incremental modifications to individual parts like pipeline stages, cores, or cache modules without affecting the rest of the system.
• Comprehensive Tooling: The distribution includes a full RISC-V compiler toolchain, a web-based graphical user interface (GUI) for system configuration, and a web-based RISC-V assembly simulator.
• Vendor-Agnostic Implementation: Hardware modules are implemented using standard synthesizable Verilog, avoiding vendor-specific blocks, which allows for deployment via RTL simulation or general FPGA-based emulation.

Technical Details

• Architecture Scope: Supports a wide range of architectures, from the simplest single-cycle processor designs to complex multi-core SoCs featuring complex memory hierarchies and integrated Networks-on-Chip (NoC).
• Exploration Parameters: The platform facilitates exploration across several dimensions, including core complexity, multi-level caching and memory organizations, system topologies, router architectures, and routing schemes.
• RTL Language: Synthesizable Verilog.
• Component Interfaces: Interfaces are explicitly designed to enable substitution; researchers can modify or replace elements such as whole cache modules, entire cores, or even individual pipeline stages.
• Deployment: Supports dual-mode deployment: software-based RTL simulation and hardware implementation via FPGA emulation.

Implications

• Accelerates RISC-V Research: BRISC-V provides researchers and academics with a powerful, pre-verified, and modular base system, dramatically reducing the time required to set up a functional, synthesizable multi-core environment for architectural testing.
• Democratization of Hardware Design: By being open-source and relying on standard, vendor-agnostic Verilog, the platform lowers the barrier to entry for developing and testing complex custom hardware based on the RISC-V ISA.
• Facilitates Targeted Innovation: The high degree of modularity is crucial for DSE, allowing researchers to isolate performance bottlenecks or test novel architectural innovations (like a new router design or cache coherence protocol) within a complete, working SoC context.
• Educational Value: The integrated compiler toolchain and web-based GUI make it an excellent resource for teaching computer architecture and hands-on hardware design projects utilizing the RISC-V instruction set.