Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Abstract

This work, titled "Big-PERCIVAL," explores the native implementation and use of 64-bit posit arithmetic (posit64) and associated quire operations by extending the PERCIVAL RISC-V core and Xposit custom ISA. Results demonstrate that posit64 achieves up to four orders of magnitude lower mean square error compared to IEEE 754 double-precision, leading to faster convergence in iterative solvers. Although ASIC and FPGA synthesis reveals a significant increase in hardware cost for these components, the substantial accuracy improvements suggest posits are a potential high-accuracy alternative for scientific computing kernels.

Report

Key Highlights

• Superior Accuracy: Posit64 arithmetic achieved up to 4 orders of magnitude lower mean square error (MSE) compared to standard IEEE 754 double-precision floating-point (doubles) in numerical benchmarks.
• Improved Convergence: This accuracy increase directly translates to a reduction in the required number of iterations for convergence in iterative solvers, such as the Conjugate Gradient method.
• Hardware Cost: Detailed FPGA and ASIC synthesis results indicate that the native implementation of 64-bit posit arithmetic and the associated specialized Quire accumulator register incurs a significant hardware area cost.
• Exploration Platform: The study was conducted by extending the PERCIVAL RISC-V core and modifying the Xposit custom RISC-V extension to support the new arithmetic standard.

Technical Details

Implications

• Validation of Posits: This research provides strong empirical evidence that posits can deliver substantially higher precision than double-precision FP using the same memory bandwidth, making them highly attractive for high-fidelity scientific simulations and High-Performance Computing (HPC).
• RISC-V Flexibility: The successful extension of the PERCIVAL core and the Xposit ISA demonstrates RISC-V's architectural agility. RISC-V serves as an ideal platform for implementing and testing non-standard, emerging arithmetic formats necessary for specialized workloads.
• Informing Hardware Design: The detailed synthesis results provide critical data regarding the trade-off between accuracy and area cost. This guides chip architects in determining if the significant hardware penalty associated with posit64 and quire is justified by the massive accuracy improvements in specific application domains.
• Challenging IEEE 754: By natively implementing and benchmarking posit64, the project furthers the effort to find more robust, high-accuracy alternatives to the dominant IEEE 754 standard, potentially shifting future architecture design paradigms in specialized accelerators.