Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS

Abstract

Basilisk is presented as the first end-to-end open-source, Linux-capable RISC-V System-on-Chip (SoC), successfully taped out utilizing IHP's open 130 nm CMOS technology. This achievement validates the capability of open-source hardware (OSHW) to produce complex, general-purpose computing silicon with a fully auditable supply chain from RTL to layout. The project included rigorous optimization of open-source Electronic Design Automation (EDA) tools like Yosys and OpenROAD, resulting in a 2.3x clock speed increase to 77 MHz and a 12% reduction in overall die area.

Report

Key Highlights

• End-to-End Open-Source Milestone: Basilisk is the first fully end-to-end open-source, Linux-capable RISC-V SoC, encompassing the entire flow from RTL to final layout.
• Open Technology Node: The SoC was taped out using IHP's publicly available 130 nm CMOS technology.
• Performance Optimization: The project significantly optimized open-source EDA tools, achieving a 2.3x increase in peak clock speed, reaching 77 MHz.
• Area Efficiency: The cell area was reduced by 1.6x (to 1.1 MGE), and the overall die area was reduced by 12% through optimized place and route.
• Fully Auditable Supply Chain: The project showcases a complete, auditable supply chain for silicon development, enhancing security and transparency.

Technical Details

• Core Architecture: Features a 64-bit RISC-V core capable of running a general-purpose operating system (Linux).
• Peripherals: Includes a comprehensive set of IO peripherals, notably a fully digital HyperRAM DRAM controller, USB 1.1 support, and VGA output.
• Design Flow: A reusable tool pipeline was created to convert the industry-grade SystemVerilog description into Verilog, necessary for compatibility with open-source tools.
• Synthesis Tool Optimization (Yosys): Logic synthesis in Yosys was optimized, resulting in the 77 MHz peak clock speed and 1.1 MGE cell area, while also reducing synthesis runtime and RAM usage.
• Place and Route Tool Optimization (OpenROAD): OpenROAD optimization enabled convergence to zero Design Rule Check (DRC) violations, increased core area utilization by 10%, and contributed to the overall 12% reduction in die area.

Implications

• Validation of OSHW Complexity: Basilisk proves that OSHW is capable of handling complex designs sufficient to run modern operating systems, moving beyond simple microcontrollers.
• Driving Open-Source EDA Maturity: The rigorous optimization effort necessary for the tapeout serves as a crucial stress test and validation for open-source EDA tools (Yosys, OpenROAD), directly leading to substantial improvements in their performance, area efficiency, and reliability (e.g., zero DRC convergence).
• Enhanced Trust and Security: By establishing a fully open and auditable path from RTL description to silicon layout, Basilisk addresses critical supply chain security concerns prevalent in proprietary hardware manufacturing.
• Accelerated Research and Customization: The full open-source nature of the design lowers the barrier to entry for academics and researchers, allowing for rapid experimentation and customization of Linux-capable RISC-V SoCs.