Abstract

The Basilisk project introduces the largest end-to-end open-source system-on-chip (SoC) to date, successfully integrating a 64-bit Linux-capable RISC-V core on a 34 mm² die. Implemented in 130 nm BiCMOS technology, this effort significantly enhanced the open-source electronic design automation (OSEDA) flow, yielding up to 2.3x timing improvement. The fabricated chip operates nominally at 62 MHz and achieves a peak energy efficiency of 18.9 DP MFLOP/s/W, validating OSEDA for complex, industry-grade designs.

Report

Basilisk SoC Technical Report

Key Highlights

• Largest OSEDA Chip: Basilisk is the largest end-to-end open-source SoC demonstrated to date (2.7 Million Gate Equivalents).
• Linux Capability: Features a 64-bit RISC-V core capable of running the Linux operating system.
• Technology Node: Fabricated in IHP's open 130 nm BiCMOS technology.
• Physical Size: The die measures 34 mm².
• Performance: Achieves 62 MHz at its nominal 1.2 V core voltage, and clocks up to 102 MHz at 1.64 V.
• Efficiency: Demonstrates a peak energy efficiency of 18.9 DP MFLOP/s/W at 0.88 V.

Technical Details

• Core Architecture: Utilizes a 64-bit RISC-V core.
• Peripheral Integration: Includes a lightweight DRAM controller capable of 124 MB/s throughput.
• I/O: Extensive input/output features, including a USB 1.1 host, dedicated video output, and a fully digital chip-to-chip (C2C) link operating at 62 Mb/s.
• Synthesis Flow Improvements: Enhancements to the Yosys-based synthesis process improved design timing by 2.3x and reduced required area by 1.6x, while also decreasing system resource consumption.
• Place and Route (P&R): Tuning of the OpenROAD P&R toolchain specifically for the design and technology led to a 12% decrease in the final die size.

Implications

• Validation of Open-Source EDA (OSEDA): The Basilisk project marks a significant milestone by demonstrating that end-to-end open-source EDA flows can successfully design and fabricate large, industry-grade chips, rather than being limited to small test designs.
• Security and Trust: By utilizing an entirely open-source flow, the project promotes zero-trust step-by-step design verification, which is crucial for secure hardware supply chains and collaborative design efforts.
• RISC-V Ecosystem Maturity: This work provides a complex, fully verifiable reference design for the open hardware community, further accelerating the adoption and maturation of the RISC-V architecture and its surrounding tool ecosystem.
• Supply Chain Diversification: The use of open standards and accessible fabrication processes (like 130nm BiCMOS) helps diversify the hardware manufacturing supply chain.