Abstract

This paper introduces BASICRV32s, an open-source framework detailing a practical microarchitectural roadmap for the RISC-V RV32I Instruction Set Architecture. The design follows an evolutionary pathway, progressing from a basic single-cycle core to a high-performance 5-stage pipelined core featuring full hazard forwarding and dynamic branch prediction. By releasing all Register-Transfer Level (RTL) code and documentation under the MIT license, BASICRV32s provides a verified, instructional pathway for the open-source hardware community.

Report

basic_RV32s Technical Analysis

Key Highlights

• Open-Source Roadmap: BASIC_RV32s is introduced as an open-source framework providing a detailed microarchitectural roadmap specifically for the RISC-V RV32I architecture.
• Evolutionary Design: The design methodology follows the classic Patterson and Hennessy approach, starting from a basic single-cycle implementation and evolving into a complex 5-stage pipelined core.
• Feature Complete: The final core implementation includes advanced features such as full hazard forwarding, dynamic branch prediction, and robust exception handling.
• Verifiable Performance: The core achieved a performance of 1.09 DMIPS/MHz when integrated into a System-on-Chip (SoC) and implemented on hardware.
• Full Reproducibility: All Register-Transfer Level (RTL) source code, signal-level logic block diagrams, and development logs are released under the permissive MIT license on GitHub.

Technical Details

• Target Architecture: RISC-V RV32I Instruction Set Architecture.
• Core Architecture: 5-stage pipeline (following the classic textbook methodology).
• Key Pipeline Features: Full data hazard forwarding and control hazard mitigation via dynamic branch prediction.
• Verification Platform: The core was integrated into an SoC, including UART communication, and verified on a Xilinx Artix-7 Field-Programmable Gate Array (FPGA).
• Performance Metrics: Achieved 1.09 Dhrystone million instructions per second per megahertz (DMIPS/MHz) running at a clock speed of 50 MHz.
• Licensing: All released materials are available under the MIT license.

Implications

• Bridging the Gap: This project effectively addresses the significant gap between theoretical computer architecture knowledge (often taught using textbooks) and practical, functional hardware implementation.
• Educational Resource: BASIC_RV32s serves as a crucial instructional pathway and reproducible reference design, lowering the barrier to entry for students and developers seeking to understand and build custom RISC-V cores.
• Strengthening Open Hardware: The release of high-quality, verified RTL and detailed documentation under a permissive license (MIT) significantly contributes to and accelerates the growth and maturity of the open-source hardware ecosystem.
• Accelerated Development: Providing a fully functional, performance-benchmarked foundational core allows other designers to quickly iterate and build upon the reliable RV32I base implementation.