Abstract

AXI-REALM is a lightweight, modular, and open-source extension to AXI4 interconnects designed to restore timing predictability and control access contention in heterogeneous real-time SoCs. Utilizing a credit-based mechanism, AXI-REALM distributes and regulates bandwidth over periodic time windows while monitoring traffic statistics and proactively preventing Denial of Service (DoS). Implemented in a RISC-V SoC, this approach recovers up to 68.2% of core performance under interference and reduces worst-case memory access latency from 264 cycles to less than eight cycles, all with minimal 2.45% area overhead.

Report

AXI-REALM: Traffic Regulation and Monitoring for Real-Time SoCs

Key Highlights

• Interconnect Solution: A lightweight, modular, and technology-independent real-time extension (AXI-REALM) for industry-standard AXI4 interconnects.
• Real-Time Focus: Specifically addresses challenges in integrated Critical Real-Time Embedded Systems (CRTESs) concerning timing predictability due to shared resource contention.
• Performance Recovery: Demonstrated recovery of 68.2% of performance for a general-purpose core suffering from interconnect interference caused by a hardware accelerator's DMA engine.
• Latency Improvement: Achieved a reduction in worst-case memory access latency from 264 cycles to below eight cycles when bandwidth was distributed in favor of the core.
• Low Overhead: Implementation introduces only 2.45% area overhead compared to the original SoC.
• Availability: The solution is available open-source.

Technical Details

• Target Protocol: Extension applied to the AXI4 interconnect standard.
• Control Mechanism: Uses a credit-based mechanism to distribute and control available bandwidth among multiple managers (masters) in a multi-subordinate system.
• Time Management: Bandwidth allocation and control are implemented over periodic time windows.
• Safety Features: Proactively prevents denial of service (DoS) from malicious actors within the system.
• Monitoring: Tracks detailed access and interference statistics for each manager, crucial for selecting optimal budget and period settings.
• Case Study Platform: Implemented into an open-source Linux-capable RISC-V SoC.
• Technology Node: Detailed performance and implementation cost assessment provided for a 12nm node.

Implications

• Timing Predictability: By introducing strict hardware-based observability and controllability over the interconnect, AXI-REALM provides a critical mechanism for ensuring timing predictability in complex heterogeneous SoCs.
• Automotive and Safety: The ability to guarantee predictable timing and prevent DoS attacks directly supports the rigorous safety and certification requirements (e.g., ISO 26262) demanded by the evolving automotive and avionics industries.
• RISC-V Adoption: The successful implementation into an open-source Linux-capable RISC-V SoC validates the architecture's compatibility and feasibility within the growing RISC-V ecosystem, providing a critical real-time infrastructure component.
• Hardware Efficiency: Minimizing buffering compared to alternative solutions and achieving extremely low area overhead (2.45%) makes AXI-REALM a highly attractive and practical solution for resource-constrained embedded systems.