Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors

Abstract

Designing Application-Specific Instruction Set Processors (ASIPs) requires the manual identification of performance-enhancing custom instructions, a process addressed by this work's new automation tool. The paper introduces CIDRE (Custom Instruction Designer for RISC-V Extensions), a front-to-back tool that automatically analyzes application hotspots and generates custom instruction suggestions for RISC-V processors. In benchmark studies, CIDRE achieved up to 2.47x acceleration on embedded workloads (Embench/MiBench) with an area increase of less than 24%, demonstrating highly efficient automated design.

Report

Key Highlights

• Automated ASIP Design: The paper introduces CIDRE (Custom Instruction Designer for RISC-V Extensions), a fully automatic, front-to-back tool for designing Application-Specific Instruction Set Processors (ASIPs).
• Problem Solved: Addresses the labor-intensive and typically manual challenge of identifying optimal custom instructions for workload acceleration.
• Significant Speedup: Achieved performance acceleration of up to 2.47x in embedded benchmarks from the Embench and MiBench suites.
• High Efficiency: The performance gains were realized while maintaining low hardware overhead, specifically less than a 24% area increase.

Technical Details

• Tool Name and Purpose: CIDRE is designed to analyze software workloads running on RISC-V architectures and automatically generate microarchitecture-aware custom instruction suggestions.
• Input/Analysis: The tool analyzes application hotspots within RISC-V software to determine instruction sequences suitable for fusion into custom instructions.
• Output Format: CIDRE generates a corresponding nML description for each custom instruction suggestion.
• Integration: The nML output enables the use of standard Electronic Design Automation (EDA) tools to accurately assess the cost (area, power) and benefit (performance) of the suggested instruction extensions.
• Target Architecture: The solution is specifically tailored for extending standard RISC-V General Purpose Processors (GPPs).

Implications

• Democratization of ASIP Design: By fully automating the custom instruction extraction process, CIDRE significantly reduces the expertise and time required to develop specialized RISC-V processors.
• Accelerated Development Cycle: Allows hardware designers to perform rapid design space exploration and quickly evaluate the performance/area trade-offs of various custom extensions.
• Leveraging RISC-V Extensibility: This tool maximizes the inherent extensibility of the RISC-V Instruction Set Architecture (ISA), enabling the creation of highly optimized cores for specific domains (e.g., embedded, IoT, AI).
• Optimizing the GPP/Accelerator Trade-off: The successful automated design of efficient ASIPs helps bridge the gap between flexible GPPs and high-performance dedicated hardware, making the specialized processor segment more practical and cost-effective.