ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors

Abstract

ASPO (Constraint-Aware Bayesian Optimization) is a novel approach designed to efficiently tune parameters for complex FPGA-based soft processors, overcoming limitations of standard Bayesian Optimization concerning categorical constraints and lengthy optimization times. The method customizes the BO covariance kernel and accelerates evaluation by leveraging disjunctive constraints and reusing FPGA synthesis checkpoints. ASPO demonstrated powerful results, reducing execution time by up to 35% and design time by 74% compared to state-of-the-art hardware optimization tools when applied to RISC-V cores like BOOM and RocketChip.

Report

Key Highlights

• Novel Optimization Method: Introduces ASPO, a customized Constraint-Aware Bayesian Optimization (BO) technique specifically tailored for optimizing FPGA-based soft processors.
• Constraint Handling: Addresses the critical weakness of standard BO by successfully incorporating constraints involving categorical parameters (e.g., choice of branch predictor or division circuit).
• Significant Acceleration: ASPO reduces the design time for complex processors like BOOM by up to 74% compared to Boomerang, a state-of-the-art hardware BO approach.
• Performance Gains: Achieves substantial performance improvements, reducing execution time for specific workloads (e.g., 'multiply' benchmark on BOOM) by up to 35% over default configurations.
• Target Architecture: Evaluated and validated across major open-source RISC-V soft processors, including RocketChip, BOOM, and EL2 VeeR.

Technical Details

• Core Methodology: Bayesian Optimization (BO) is employed, but its mathematical mechanism is customized for FPGA soft-processor design challenges.
• Categorical Constraint Solution: ASPO leverages a disjunctive form to enable BO to correctly handle constraints that mix continuous and categorical parameters.
• Kernel Customization: The approach utilizes a novel customized BO covariance kernel specifically designed to navigate the configuration space of soft processors.
• Design Time Reduction: Acceleration is achieved through two primary mechanisms:
  1. Penalizing the BO acquisition function based on the potential evaluation time required for a configuration.
  2. Reusing FPGA synthesis checkpoints from previously evaluated configurations.
• Evaluation Metrics: Optimization was based on performance metrics derived from running seven distinct RISC-V benchmarks.

Implications

• Democratization of HPC/FPGA: ASPO significantly accelerates the design exploration space for soft processors, making it feasible to rapidly customize complex, high-performance RISC-V cores (like BOOM) for specific FPGA deployment constraints.
• Advanced RISC-V Customization: It provides a crucial tool for the RISC-V ecosystem, allowing designers to automatically find configurations that maximize performance and minimize area/power, which is vital for competitive soft processor implementation.
• Machine Learning in EDA: This work advances the intersection of Machine Learning and Electronic Design Automation (EDA) by solving practical, high-dimensional configuration problems that previous BO methods could not handle efficiently, specifically those involving complex interdependencies between discrete design choices.