Architect in the Loop Agentic Hardware Design and Verification

Abstract

This paper proposes an "Architect in the Loop" agentic framework that automates the systematic and hierarchical design and verification of complex digital hardware, particularly processors. The methodology utilizes a combination of reasoning (Gemini-Pro) and non-reasoning (GPT-5-mini) Large Language Models (LLMs) to decompose designs, generate HDL, and create cocotb testbenches, incorporating human guidance for crucial debugging and synthesis steps. The system successfully demonstrated the development of both a LEGv8-like processor, synthesized onto an FPGA, and a RISC-V 32-bit processor cost-effectively, requiring only about one million inference tokens per design.

Report

Key Highlights

• Agentic Automation: Introduction of an automated agentic system for processor-level hardware design and verification.
• Architect in the Loop: The system maintains human engineers for critical tasks, specifically debugging and synthesis, ensuring design integrity.
• Hierarchical Approach: The methodology systematically utilizes best practices like hierarchical and modular design decomposition.
• Demonstrated Success: Two simple processors were successfully designed and verified: a LEGv8-like core (synthesized and programmed on a DE-10 Lite FPGA) and a RISC-V 32-bit core.
• Cost Efficiency: The process is cost-effective, typically requiring around one million inference tokens per processor, utilizing general-purpose LLMs without needing specialized hardware.

Technical Details

• Core Architecture: The agent is designed to break down high-level design specifications into sub-components.
• Design Generation: The agent generates Hardware Description Language (HDL) code for components.
• Verification: The agent automatically generates cocotb tests for comprehensive verification.
• LLM Configuration: The system employs a mixture of model types based on task complexity, including reasoning models (e.g., Gemini-Pro) and non-reasoning models (e.g., GPT-5-mini).
• Implementation Target: The LEGv8-like processor was verified and synthesized for the DE-10 Lite FPGA platform.
• Scalability: The approach is noted as scalable, with future experimentation planned for System-on-Chip (SoC) designs.

Implications

• Acceleration of RISC-V Development: This methodology drastically speeds up the prototyping phase for custom RISC-V instruction set architectures (ISAs) or specific core implementations, reducing the dependency on manual HDL coding.
• Lowering Design Barriers: By leveraging cost-effective, general-purpose LLMs, the framework democratizes complex hardware design, allowing smaller teams or academic researchers to iterate on processor architectures more rapidly.
• Enhanced Verification Quality: The automated generation of industry-standard cocotb testbenches promises more thorough and consistent verification relative to manual ad-hoc testing.
• Facilitating Complex Designs: The validation of the hierarchical, modular approach suggests a viable path toward automating the design of entire RISC-V-based SoCs, addressing the escalating complexity demands in the semiconductor industry.