AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors

Abstract

AraXL is a novel, ultra-wide RISC-V V vector processor designed to overcome the physical scalability limitations, such as wire dominance, found in state-of-the-art vector designs for HPC and ML applications. It achieves unprecedented scaling by employing a modular architecture with a distributed and hierarchical interconnect, successfully supporting up to 64 parallel vector lanes. Implemented in a 22-nm technology, the 64-lane AraXL demonstrates a high peak performance of 146 GFLOPs and impressive energy efficiency of 40.1 GFLOPs/W.

Report

Key Highlights

• Ultra-Wide Scalability: AraXL supports up to 64 parallel vector lanes, significantly exceeding the current industry scaling limitation of approximately 8 lanes for double-precision FPUs.
• Physical Constraint Solution: The architecture directly addresses and resolves physical implementation challenges (e.g., wire dominance) that plague wide vector processors through a distributed and hierarchical interconnect design.
• High Performance: Achieves a peak performance of 146 GFLOPs on computation-intensive HPC/ML kernels.
• Energy Efficiency: Delivers an energy efficiency of 40.1 GFLOPs/W.
• ISA Compliance: Reaches the maximum Vector Register File (VRF) size of 64 Kibit/vreg permitted by the RISC-V V 1.0 ISA specification.

Technical Details

• Architecture: Modular and scalable 64-bit RISC-V V vector architecture.
• Scaling Mechanism: Uses a distributed and hierarchical interconnect structure, which is the key enabler for physical scalability up to 64 lanes.
• Technology Node: Implemented in a 22-nm technology node.
• Operating Point: Achieved reported efficiency at 1.15 GHz (TT, 0.8V).
• Resource Utilization: Demonstrated high FPU utilization (>99%) during kernel execution.
• Area Efficiency: The 64-lane AraXL instance required only 3.8x the area of a smaller 16-lane instance, indicating highly efficient physical scaling.

Implications

• Advancing RISC-V Vector Adoption: AraXL proves that the RISC-V V ISA can be successfully deployed in high-end, physically scalable hardware, making RISC-V a viable contender for demanding HPC and large-scale ML acceleration.
• Enabling Long Vector Processing: By supporting the maximum VRF size and 64 lanes, AraXL is optimized for the increasingly massive data parallelism found in modern AI and scientific computing, where long vectors are crucial.
• New Design Paradigm: The hierarchical interconnect approach sets a precedent for how future ultra-wide processors can be physically designed, mitigating the historical performance bottlenecks associated with wiring complexity in large-scale parallel units.
• Efficiency Benchmark: The high GFLOPs/W metric reinforces the feasibility of achieving high performance in complex data processing tasks while maintaining excellent energy efficiency, crucial for both data centers and edge accelerators.