AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance

Abstract

This work introduces AraOS, an integrated environment enabling full operating system (Linux) support for the open-source Ara2 RISC-V vector processor by sharing the Memory Management Unit (MMU) of the CVA6 scalar core. The research specifically analyzes the performance overhead incurred by virtual-to-physical address translation on vector workloads like matrix multiplication. The authors demonstrate that with a sufficient Translation Lookaside Buffer (TLB) size (16 entries or more), virtual memory overhead remains below 3.5%, while achieving significant performance gains up to 3.2x over scalar execution.

Report

AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance

Key Highlights

• OS Integration for Vector Unit: The study successfully developed AraOS, adding full OS (Linux) support to the bare-metal open-source Ara2 vector processor.
• Virtual Memory Overhead Analysis: The primary goal was to quantify the performance cost of virtual-to-physical address translation when running vector operations under a complex OS environment.
• Minimal Overhead: Experimental results show that the virtual memory overhead remains minimal, consistently below 3.5%, provided the shared MMU's Translation Lookaside Buffer (TLB) has at least 16 entries.
• Performance Gains: Benchmarking a 2-lane AraOS instance with the RiVEC benchmark suite demonstrated peak average speedups of 3.2x compared to scalar-only execution.

Technical Details

• Target Architecture: RISC-V Vector (RVV) ISA extension.
• Hardware Components: The system integrates the open-source Ara2 vector processor, which relies on the CVA6 scalar core for instruction dispatch.
• MMU Sharing: AraOS utilizes the MMU of the CVA6 scalar core for virtual memory management.
• Platform: Integration was performed within the open-source Cheshire SoC platform.
• Evaluation Methodology: Performance evaluation involved benchmarking matrix multiplication kernels across various problem sizes and specific configurations of the CVA6 MMU TLB.
• Benchmark Suite: The RiVEC open-source benchmark suite designed for RVV architectures was used to measure overall speedup.

Implications

• Closing the Data Gap: This research addresses a crucial gap in the RISC-V ecosystem by providing hard performance data for open-source RVV processors operating under a full-fledged operating system (Linux), rather than in a bare-metal environment.
• Validation for System Design: The findings validate that complex vector units can be effectively integrated into standard SoC architectures requiring virtual memory, confirming that VMM does not introduce prohibitive performance penalties if TLB resources are adequately provisioned.
• ** thúc đẩy RVV Adoption:** Demonstrating manageable overhead and significant speedups (3.2x) under realistic OS conditions encourages the broader adoption of the RISC-V Vector ISA in production environments, including high-performance computing and complex embedded systems.
• Open-Source Contribution: The creation of AraOS contributes new OS support and system integration knowledge back to the growing open-source RISC-V hardware community.