ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework

Abstract

ANDROMEDA is an FPGA-based framework designed for the exploration and optimization of complex RISC-V Multiprocessor Systems-on-Chip (MPSoCs). It enables computer architects to vary and observe the performance trade-offs of critical parameters, including core count, memory subsystems, and Network-on-Chip (NoC) configurations. The framework is emulated on the Synopsys HAPS-80D Dual FPGA platform and successfully validates its utility using demanding benchmarks like STREAM and N-body simulations.

Report

Key Highlights

• RISC-V MPSoC Exploration: Introduces ANDROMEDA, a framework dedicated to exploring various configurations of RISC-V based Multiprocessor Systems-on-Chip (MPSoCs).
• Parameter Balancing: Focuses on the crucial task of balancing core count, memory subsystems, and Network-on-Chip (NoC) parameters to achieve desired application performance.
• FPGA Emulation: The entire exploration process is conducted via emulation on the high-end Synopsys HAPS-80D Dual FPGA platform.
• Demonstrated Efficacy: The framework's utility is proven by its ability to quickly identify efficient parameters when executing computationally intensive benchmarks.

Technical Details

• Target Architecture: Multiprocessor System-on-Chip (MPSoC) featuring RISC-V cores.
• Variable Components: The framework supports the exploration of key architectural variables, including the number of processor cores, specific memory subsystem characteristics, and NoC configurations.
• Platform: Synopsys HAPS-80D Dual FPGA platform is used for physically emulating the different MPSoC configurations.
• Validation Benchmarks: Performance observation and analysis were conducted using standard parallel computational tasks, specifically STREAM, matrix multiplication, and N-body simulations.
• Goal: To quantify performance penalties and gains resulting from configuration changes.

Implications

• Accelerated Design Cycle: ANDROMEDA provides a vital tool for computer architects, enabling the rapid prototyping and testing of numerous RISC-V MPSoC configurations in hardware emulation before committing to expensive ASIC fabrication.
• Optimizing Performance: By offering quick identification of optimal parameters, the framework directly addresses the exponential increase in computational requirements of modern consumer electronics, ensuring efficient utilization of resources.
• Advancing RISC-V Adoption: The existence of robust exploration frameworks like ANDROMEDA encourages greater complexity and adoption of the RISC-V ISA in sophisticated, high-core-count computing environments, validating its scalability potential.