Abstract

This paper introduces an innovative analytical framework for 3D mixed-size placement in heterogeneous, face-to-face (F2F) bonded 3D ICs, effectively integrating large macros and standard cells. The method employs a dedicated density model, a bistratal wirelength model, a novel 3D preconditioner, and a Mixed-Integer Linear Programming (MILP) formulation for optimal macro rotation. Leveraging full-scale GPU acceleration, the framework achieves a 5.9% quality score improvement and 4.0x runtime speedup over the ICCAD 2023 contest winner, with validation extending to modern RISC-V designs.

Report

Structured Report: Analytical Heterogeneous Die-to-Die 3D Placement with Macros

Key Highlights

• Focus Area: Innovative 3D mixed-size placement methodology addressing heterogeneous die-to-die integration (specifically face-to-face (F2F) bonded 3D ICs).
• Performance Benchmark: Achieved a significant 5.9% quality score improvement compared to the first-place winner of the ICCAD 2023 contest.
• Efficiency: Demonstrated a 4.0x runtime speedup over the previous state-of-the-art solution.
• Generalizability: The framework’s superiority and practical application were validated using modern RISC-V designs, alongside standard ICCAD benchmarks.
• Core Innovation: Utilization of an analytical framework incorporating specialized 3D models and optimization techniques for handling complex macro and standard cell interactions.

Technical Details

• Placement Type: Analytical placement framework designed for 3D integrated circuits involving heterogeneous dies.
• Modeling: Proposes two dedicated models for effective placement:
  • A specialized density model to manage the spatial requirements in 3D.
  • A bistratal wirelength model to accurately estimate connectivity costs across the die stack.
• Macro Handling: Introduces a novel 3D preconditioner to specifically resolve the challenging topological and physical gap between the placement constraints of large macros and small standard cells.
• Optimization: Utilizes a Mixed-Integer Linear Programming (MILP) formulation to determine the optimal rotation of macros, minimizing overall wirelength.
• Acceleration: The entire framework is implemented with full-scale GPU acceleration through:
  • An adaptive 3D density accumulation algorithm.
  • An incremental wirelength gradient algorithm.

Implications

• Advancing 3D IC Design: This work provides a critical EDA tool needed to realize the potential of advanced 3D heterogeneous integration and chiplet architectures. Efficiently placing macros (like large memory blocks or specialized IP) in a 3D context is crucial for maximizing performance and density.
• Faster Design Cycles: The 4.0x speedup dramatically reduces the time required for the placement stage of the design flow, accelerating the development and time-to-market for complex 3D systems.
• Impact on RISC-V Ecosystem: The explicit validation on "modern RISC-V designs" highlights the framework's relevance to the open-source hardware movement. As RISC-V designs increasingly push into high-performance computing (HPC) and need to utilize 3D stacking for competitive performance, this specialized placement tool becomes vital for optimizing those implementations.
• Quality of Results: The improved quality score suggests resulting chips will exhibit better wirelength characteristics, correlating to lower power consumption and higher operating frequencies in the final hardware product.