An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation

Abstract

This paper introduces an integrated UVM-TLM co-simulation framework designed to efficiently verify complex RISC-V processors by simultaneously evaluating functional correctness and performance. The methodology employs a configurable Transaction-Level Model (vmodel) of a superscalar, out-of-order RISC-V core, featuring credit-based pipeline flow control. This environment unifies functional verification using the Spike ISA simulator with early performance assessment via benchmarks like CoreMark, demonstrating significant simulation speedup over traditional RTL approaches.

Report

Key Highlights

• Integrated Co-Simulation: Development of a unified framework leveraging Universal Verification Methodology (UVM) and Transaction-Level Modeling (TLM).
• Dual Focus: Designed to concurrently evaluate both functional correctness and early-stage performance of RISC-V processors.
• Simulation Efficiency: Achieved significant simulation speedup compared to slower, cycle-level Register-Transfer Level (RTL) verification methods.
• Configurable Model: The core of the framework is a configurable UVM-TLM model (vmodel) of a complex RISC-V architecture.

Technical Details

• Modeling Target: The framework models a superscalar, out-of-order RISC-V core microarchitecture.
• Modeling Technique: Key microarchitectural behavior is modeled using credit-based pipeline flow control to manage simulation fidelity without requiring full cycle-level precision.
• Functional Verification Tool: Functional correctness is verified through co-simulation against the industry-standard reference model, the Spike ISA simulator.
• Performance Evaluation: Performance assessment is conducted using industry benchmarks, specifically CoreMark, orchestrated within the UVM environment.
• Fidelity Trade-off: The methodology prioritizes simulation efficiency and acceptable fidelity suitable for architectural exploration over achieving exact cycle-level precision.

Implications

• Accelerated Design Iterations: By offering significant simulation speedup over RTL, the framework dramatically shortens verification cycles, accelerating the development and iteration of complex RISC-V designs.
• Enhanced Verification Coverage: The unified environment allows verification teams to easily link functional test cases with performance metrics, enhancing overall verification coverage and providing a holistic view of design quality.
• Early Architectural Exploration: Enabling early-stage performance assessment using TLM models allows designers to explore and validate architectural trade-offs efficiently before significant resources are committed to detailed RTL implementation.
• Growing Ecosystem Support: This efficient, integrated methodology is critical for managing the increasing complexity of processors within the rapidly burgeoning RISC-V ecosystem.