An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research

Abstract

This paper introduces an open-source, FPGA-based hardware-software framework designed to streamline side-channel analysis (SCA) research on IoT-class computing platforms. The system features a RISC-V System-on-Chip (SoC) and integrates an ad-hoc debug infrastructure optimized for attack observability and controllability. The goal is to provide researchers with a stable foundation, including a suite of state-of-the-art attacks and countermeasures, accelerating the development and evaluation of robust security solutions.

Report

Key Highlights

• Open-Source Framework: The entire hardware-software platform, including the SoC design, scripts, and security suites, is released as open-source.
• FPGA Target: The framework is explicitly designed for deployment and research on FPGA hardware.
• IoT-Class SoC: It provides a realistic System-on-Chip (SoC) environment representative of Internet of Things (IoT) devices.
• RISC-V Core: The computing platform is based on a RISC-V CPU architecture.
• Comprehensive Package: The release includes the SoC, configuration scripts, and a suite of pre-implemented, state-of-the-art SCA attacks and countermeasures for immediate security assessment.

Technical Details

• Architecture: IoT-class System-on-Chip (SoC) incorporating a RISC-V CPU.
• SCA Facilitation: Utilizes an ad-hoc debug infrastructure specifically engineered to provide high observability and controllability during side-channel attacks.
• Countermeasure Support: Dedicated hardware and software features are included to streamline the deployment of defenses.
• Hardware Feature: Includes a DFS actuator (Dynamic Frequency Scaling) to evaluate frequency-based countermeasures.
• Software Feature: Provides support for FreeRTOS, enabling research within a common embedded operating system environment.
• Workflow: The framework includes specific scripts for platform configuration, compiling target applications, and automated security assessment.

Implications

• Accelerating Security Research: By offering a sound and stable platform, the framework reduces the overhead associated with setting up complex test environments, allowing designers and researchers to focus strictly on developing and testing novel SCA countermeasures and attacks.
• RISC-V Security Hardening: The open-source nature and integration of a RISC-V core provide a crucial tool for the community to rigorously test and harden the security of RISC-V implementations, which is essential for its widespread adoption in security-sensitive domains like IoT.
• Addressing IoT Constraints: This framework directly aids developers constrained by tight time-to-market deadlines and budgets typical of the IoT industry, enabling robust security evaluation early in the device lifecycle.
• Fostering Collaboration: The open-source release is intended to foster adoption and novel developments, standardizing the foundation upon which future hardware security research can be built.