AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing

Abstract

AiTPO presents a novel framework utilizing a heterogeneous KAN-UNet network architecture designed for highly accurate timing prediction and optimization during the critical global routing phase of IC design. By integrating the localized function approximation of Kolmogorov-Arnold Networks (KANs) with the spatial feature extraction of a UNet, the system offers superior predictive power over traditional methods. This innovation aims to significantly accelerate design closure and improve the final performance metrics (PPA) of complex integrated circuits.

Report

AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing

Key Highlights

• Novel Framework: Introduces AiTPO, a specific methodology focused on enhancing the performance of physical design tools.
• Critical Stage Focus: Targets timing prediction and optimization specifically during the Global Routing stage, a highly influential phase for final chip timing closure.
• Hybrid Architecture: Employs a unique heterogeneous deep learning model named KAN-UNet, merging two distinct network paradigms.
• Improved Accuracy: The primary goal is to leverage machine learning (ML) to overcome the inherent inaccuracies and long runtimes associated with traditional static timing analysis (STA) during early physical design stages.

Technical Details

• Architecture: KAN-UNet Heterogeneous Network.
  • UNet Component: Functions as the backbone for spatial data processing. UNets are ideal for grid-based inputs (like routing density maps or blockage information) because they efficiently capture multi-scale spatial features required to understand connectivity and congestion in IC layouts.
  • KAN Component (Kolmogorov-Arnold Networks): Used for function approximation. KANs are known for potentially offering better accuracy, faster convergence, and interpretability compared to standard MLPs, specifically beneficial for complex, non-linear timing models.
• Application: The network processes layout features (e.g., congestion, layer usage, net topology) to predict complex timing metrics (e.g., critical path delays, net delays) much faster than full parasitic extraction and STA runs.
• Optimization Loop: AiTPO likely integrates the predictive model into an optimization loop, guiding the global router to minimize predicted timing violations before moving to detailed routing.

Implications

• Enhanced PPA (Power, Performance, Area): Accurate, fast timing prediction allows engineers to make better routing decisions earlier in the design flow, directly leading to better overall Power, Performance, and Area outcomes for resulting silicon.
• Acceleration of Design Cycles: Traditional timing closure is highly iterative and time-consuming. Replacing slower, full-stack analysis with rapid, ML-driven prediction significantly reduces the time needed for physical design iterations, accelerating time-to-market.
• Support for Advanced Nodes and Complexity: As modern designs, including advanced RISC-V SoCs, transition to smaller process nodes (e.g., 5nm, 3nm) and incorporate complex structures (e.g., 3D stacking), timing closure complexity explodes. ML solutions like AiTPO become essential tools for managing these challenges.
• Advancement in EDA Tools: This work signals the growing maturity of advanced ML techniques (like KANs) within the Electronic Design Automation (EDA) ecosystem, indicating a future where neural networks are integral to core chip design algorithms.