AiDRC: Accelerating Detailed Routing by AI-Driven Design Rule Violation Prediction and Checking

Abstract

AiDRC is a novel methodology designed to accelerate the computationally intensive detailed routing stage in VLSI design. It leverages sophisticated AI techniques to predict potential Design Rule Violations (DRVs) before they occur during the routing process. By integrating AI-driven prediction and checking directly into the routing flow, AiDRC aims to significantly speed up physical design closure and improve overall routing quality.

Report

AiDRC: Accelerating Detailed Routing by AI-Driven Design Rule Violation Prediction and Checking

Key Highlights

• Acceleration of Detailed Routing: The primary goal of AiDRC is to address the computational bottleneck associated with detailed routing, a critical and time-consuming stage in IC physical design.
• AI-Driven Prediction: AiDRC distinguishes itself from traditional methods by utilizing AI/ML models to proactively predict potential violation hot spots rather than relying solely on post-layout Design Rule Checking (DRC).
• Enhanced Efficiency: By predicting and mitigating DRVs in real-time during the routing process, the system significantly reduces the number of costly iterative routing attempts and subsequent fixing cycles.
• Improved Convergence: The methodology facilitates faster convergence to a DRC-clean layout, minimizing time-to-tapeout for complex chip designs, particularly those leveraging advanced technology nodes.

Technical Details

• Methodology: The system integrates a trained machine learning model (likely based on spatial analysis using architectures like CNNs or GNNs) directly into the detailed routing engine.
• Input Data and Analysis: The AI model analyzes the local routing context, including surrounding wire segments, obstacles, and current placement data, providing real-time feedback.
• Prediction Output: The model outputs a probability score or classification that identifies the likelihood of a DRV if a potential wire segment is placed at a specific location.
• Integration: This prediction acts as a powerful heuristic, guiding the router's search algorithm to choose paths that inherently comply with complex manufacturing rules, accelerating the achievement of design closure.

Implications

• Advancing EDA Tools: AiDRC represents a major step in the integration of powerful machine learning methodologies into core Electronic Design Automation (EDA) flows, fundamentally changing how physical synthesis is performed.
• Supporting Complex Design: Faster and more efficient routing is vital for developing modern, high-core count processors and specialized accelerators. This efficiency directly benefits the proliferation of complex architectures, including those in the rapidly expanding RISC-V ecosystem.
• Scalability for Advanced Nodes: As fabrication moves to 7nm, 5nm, and 3nm, design rules become exponentially complex. AI-driven prediction is essential for managing this complexity computationally, ensuring the detailed routing stage remains fast and tractable.
• Economic Impact: Reducing physical design cycle time decreases non-recurring engineering (NRE) costs and accelerates market entry, fostering greater innovation and competition in custom silicon development.