Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration

Abstract

Acore-CIM introduces a self-calibrated mixed-signal Compute-In-Memory (CIM) System-on-Chip (SoC) designed to overcome the integration and reliability challenges of analog AI accelerators. The architecture pairs dense SRAM weight storage with linear resistors for multi-bit computation, integrating a control processor using an open-source testing strategy. Crucially, the system employs automated RISC-V controlled on-chip calibration, successfully improving the compute Signal-to-Noise Ratio (SNR) by 25% to 45% and reaching 18–24 dB.

Report

Key Highlights

• Primary Innovation: Acore-CIM, a self-calibrated mixed-signal CIM accelerator SoC, addressing reliability and integration issues in AI hardware.
• Calibration Mechanism: Utilizes an automated RISC-V controlled on-chip calibration system for enhanced accuracy.
• Performance Gain: The calibration process significantly improved compute SNR by 25% to 45%, achieving robust figures between 18 dB and 24 dB.
• Integration Solution: The architecture combines the density and programmability of SRAM-based weight storage with multi-bit computation using linear resistors.
• Fabrication: The proof-of-concept SoC was fabricated in 22-nm FDSOI technology.

Technical Details

• CIM Architecture: The system employs a mixed-signal CIM core that leverages existing SRAM for efficient weight storage while utilizing linear resistors for the analog computation steps (multi-bit processing).
• Control Processor: Integration relies on an embedded RISC-V processor dedicated to controlling the self-calibration routines and managing the end-to-end AI acceleration flow.
• Reliability Improvement: The self-calibration addresses the susceptibility of analog circuits to variations, which typically lead to computation errors and degraded neural network accuracy.
• Programming Strategy: The work includes an open-source programming and testing strategy to facilitate the use and deployment of the CIM system.
• Extensibility: The design demonstrates potential for extension to integrate recent high-density linear resistor technologies for future performance scaling.

Implications

• Reliability in Analog AI: Acore-CIM provides a crucial breakthrough by demonstrating a practical, effective method (RISC-V self-calibration) to stabilize analog CIM accuracy, which is a major hurdle for large-scale adoption of mixed-signal accelerators.
• RISC-V Ecosystem Adoption: This research solidifies RISC-V’s role beyond general-purpose computing, establishing it as a key, flexible control processor for specialized, highly sensitive hardware like mixed-signal CIM systems.
• Standardization and Integration: By offering an open-source programming and testing strategy, the work lowers the barrier to entry for developing end-to-end AI computing systems that rely on customized mixed-signal components.
• Practical Hardware Path: The use of SRAM combined with linear resistors offers a more efficient and easier-to-program alternative compared to the commonly explored but more complex emerging Non-Volatile Memory (eNVM) CIM counterparts, accelerating the path to commercial viability.