Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation

Abstract

This paper presents a novel multi-purpose simulator that accelerates cycle-level full-system simulation of multi-core RISC-V systems using binary translation. The tool successfully addresses the perennial trade-off between simulation accuracy and performance, achieving speeds nearly 100 times faster than traditional detailed cycle-accurate models. The simulator features runtime switching between highly performant functional mode (outperforming QEMU) and accurate cycle-level timing mode, which operates at more than 20 MIPS.

Report

Key Highlights

• Acceleration Method: Introduces a novel multi-purpose simulator utilizing binary translation to accelerate full-system simulation.
• Performance Breakthrough: Achieves cycle-level simulation speeds greater than 20 MIPS for multi-core RISC-V processors.
• Speed Advantage: The cycle-level speed is approximately 100 times faster than more detailed cycle-accurate models (e.g., RTL simulators or gem5).
• Runtime Flexibility: The simulator supports dynamic switching between high-speed functional simulation mode and cycle-level timing mode at runtime.

Technical Details

• Target System: Multi-Core RISC-V systems.
• Simulation Modes: Supports both functional simulation (which is stated to outperform QEMU) and cycle-level timing simulation.
• Methodology: The core innovation lies in exploiting binary translation to boost simulation performance while maintaining necessary cycle-level accuracy.
• Comparison Benchmarks: The simulator is positioned as a middle ground between extremely slow, highly accurate tools (RTL simulators, gem5) and extremely fast, low-fidelity functional simulators (QEMU).

Implications

• Improved Design Exploration: By providing a highly performant yet accurate model, the simulator significantly aids in the rapid design space exploration and verification of complex multi-core RISC-V architectures.
• Bridging the Gap: It resolves the long-standing challenge of balancing performance and accuracy, enabling researchers to run large benchmarks that were previously prohibitively slow on detailed cycle-accurate models.
• Ecosystem Development: The tool enables quicker iteration cycles for both hardware architects and software developers working on the expanding RISC-V ecosystem, especially for systems involving complex multi-core interactions that functional simulators cannot accurately model.